LAN9250 datasheet(41/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 41

LAN9250

PHY reset completion can be determined by polling the PHY_RST bit in the Reset Control Register (RESET_CTL) or

the Soft Reset bit in the PHY Basic Control Register (PHY_BASIC_CONTROL) until it clears. Under normal conditions,

the PHY_RST and Soft Reset bit will clear approximately 102 uS after the PHY reset occurrence.

In addition to the methods above, the PHY is automatically reset after returning from a PHY power-down mode. This

reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer to Section

12.2.10, "PHY Power-Down Modes," on page 222 for additional information.

Refer to Section 12.2.12, "Resets," on page 224 for additional information on PHY resets.

Host MAC Sub-System Reset

A Host MAC sub-system reset is performed by setting the HMAC_RST bit in the Reset Control Register (RESET_CTL).

In addition, the MAC address of the Host MAC is reloaded from the EEPROM, using the device EEPROM loader.

This will reset the Host MAC and FIFOs, including:

•MAC

• Address Filtering

• Wake-On-LAN

• RX Checksum Offload

• TX Checksum Offload

• Energy Efficient Ethernet Control and Counters

•FIFOs

• Flow Control Logic

The following registers and register fields will be reset:

• All registers described in Section 11.14, "Host MAC & FIFO Interface Registers," on page 176

Note:

The HBI register locks associated with these register are also reset.

• All registers described in Section 11.15, "Host MAC Control and Status Registers," on page 192



The EEPROM Controller Busy (EPC_BUSY) and Configuration Loaded (CFG_LOADED) bits in the

EEPROM Command Register (E2P_CMD) (set and cleared respectively)

Note:

The bits in the Interrupt Status Register (INT_STS) listed in Section 8.2.4, "Host MAC Interrupts" are not

reset.

Note:

Host MAC and FIFO related bits in the Hardware Configuration Register (HW_CFG) are not reset.

Host MAC reset completion can be determined by polling the HMAC_RST bit in the Reset Control Register

(RESET_CTL) until it clears.

1588 Reset

A reset of all 1588 related logic, including the clock/event generation and 1588 TSUs, is performed by setting the 1588

Reset (1588_RESET) bit in the 1588 Command and Control Register (1588_CMD_CTL).

The registers described in Section 14.0, "IEEE 1588," on page 298 are reset.

No other modules of the device are affected by this reset.

1588 reset completion can be determined by polling the 1588 Reset (1588_RESET) bit in the 1588 Command and Con-

trol Register (1588_CMD_CTL) until it clears.

Note:

When using the Soft Reset bit to reset the PHY, register bits designated as NASR are not reset.

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