LAN9250 datasheet(35/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 35

LAN9250

5.2.2

BACK-TO-BACK READ CYCLES

There are also restrictions on specific back-to-back host read operations. These restrictions concern reading specific

registers after reading a resource that has side effects. In many cases there is a delay between reading the device, and

the subsequent indication of the expected change in the control and status register values.

In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been estab-

lished. These periods are specified in Table 5-3. The host processor is required to wait the specified period of time

between read operations of specific combinations of resources. The wait period is dependent upon the combination of

registers being read.

Performing “dummy” reads of the Byte Order Test Register (BYTE_TEST) register is a convenient way to guarantee that

the minimum wait time restriction is met. Table 5-3 below also shows the number of dummy reads that are required for

back-to-back read operations. The number of BYTE_TEST reads in this table is based on the minimum timing for Tcyc

Receive Configuration Regis-

ter (RX_CFG)

Interrupt Configuration Regis-

ter (IRQ_CFG)

Interrupt Status Register

(INT_STS)

Interrupt Configuration Regis-

ter (IRQ_CFG)

Power Management Control

165

Power Management Control

170

Interrupt Configuration Regis-

ter (IRQ_CFG)

160

Interrupt Status Register

(INT_STS)

General Purpose Timer Con-

figuration Register

(GPT_CFG)

General Purpose Timer Con-

figuration Register

(GPT_CFG)

170

General Purpose Timer Count

1588 Command and Control

Interrupt Configuration Regis-

ter (IRQ_CFG)

Interrupt Status Register

(INT_STS)

1588 Interrupt Status Register

(1588_INT_STS)

1588 Interrupt Status Register

(1588_INT_STS)

Interrupt Configuration Regis-

ter (IRQ_CFG)

1588 Interrupt Enable Regis-

ter (1588_INT_EN)

Interrupt Configuration Regis-

ter (IRQ_CFG)

General Purpose I/O Interrupt

Status and Enable Register

(GPIO_INT_STS_EN)

Interrupt Configuration Regis-

ter (IRQ_CFG)

TABLE 5-2:

READ AFTER WRITE TIMING RULES (CONTINUED)

After Writing...

wait for this many

nanoseconds...

or Perform this many

Reads of BYTE_TEST…

(assuming Tcyc of 45ns)

before reading...

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