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LAN9250 Datasheet(PDF) 71 Page - Microchip Technology |
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LAN9250 Datasheet(HTML) 71 Page - Microchip Technology |
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71 / 421 page  2015 Microchip Technology Inc. DS00001913A-page 71 LAN9250 7 TX Status FIFO Level Interrupt (TSFL) This interrupt is generated when the TX Status FIFO reaches the pro- grammed level in the TX Status Level field of the FIFO Level Interrupt Reg- ister (FIFO_INT). R/WC 0b 6 RX Dropped Frame Interrupt (RXDF_INT) This interrupt is issued whenever a receive frame is dropped by the Host MAC. R/WC 0b 5 RESERVED RO - 4 RX Status FIFO Full Interrupt (RSFF) This interrupt is generated when the RX Status FIFO is full and another sta- tus write is attempted by the device. R/WC 0b 3 RX Status FIFO Level Interrupt (RSFL) This interrupt is generated when the RX Status FIFO reaches the pro- grammed level in the RX Status Level field of the FIFO Level Interrupt Reg- ister (FIFO_INT). R/WC 0b 2:1 RESERVED RO - 0 RESERVED RO - Bits Description Type Default |
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