LAN9250 datasheet(53/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 53

LAN9250

6.4

Device Ready Operation

The device supports a Ready status register bit that indicates to the Host software when the device is fully ready for

operation. This bit may be read via the Power Management Control Register (PMT_CTRL) or the Hardware Configura-

tion Register (HW_CFG).

Following power-up reset, RST# reset, or digital reset (see Section 6.2, "Resets"), the Device Ready (READY) bit indi-

cates that the device has read, and is configured from, the contents of the EEPROM.

An EEPROM RELOAD command, via the EEPROM Command Register (E2P_CMD), will restart the EEPROM Loader,

temporarily causing the Device Ready (READY) to be low.

A Host MAC reset, via the Reset Control Register (RESET_CTL), will utilize the EEPROM Loader, temporarily causing

the Device Ready (READY) to be low.

Entry into any power savings state (see Section 6.3.4, "Chip Level Power Management") other than D0 will cause

Device Ready (READY) to be low. Upon wake-up, the Device Ready (READY) bit will go high once the device is

returned to power savings state D0 and the PLL has re-stabilized.

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