LAN9250 datasheet(74/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 74

 2015 Microchip Technology Inc.

9.0

HOST BUS INTERFACE

9.1

Functional Overview

The Host Bus Interface (HBI) module provides a high-speed asynchronous slave interface that facilitates communica-

tion between the device and a host system. The HBI allows access to the System CSRs and internal FIFOs and mem-

ories and handles byte swapping based on the endianness select.

The following is an overview of the functions provided by the HBI:

• Address bus input: Two addressing modes are supported. These are a multiplexed address / data bus and a de-

multiplexed address bus with address index register accesses. The mode selection is done through a configura-

tion input.

• Selectable data bus width: The host data bus width is selectable. 16 and 8-bit data modes are supported. This

selection is done through a configuration input. The HBI performs BYTE and WORD to DWORD assembly on

write data and keeps track of the BYTE / WORD count for reads. Individual BYTE access in 16-bit mode is not

supported.

• Selectable read / write control modes: Two control modes are available. Separate read and write pins or an

enable and direction pin. The mode selection is done through a configuration input.

• Selectable control line polarity: The polarity of the chip select, read / write and address latch signals is select-

able through configuration inputs.

• Dynamic Endianness control: The HBI supports the selection of big and little endian host byte ordering based

on the endianness signal. This highly flexible interface provides mixed endian access for registers and memory.

Depending on the addressing mode of the device, this signal is either configuration register controlled or as part of

the strobed address input.

• Direct FIFO access: A FIFO direct select signal directs all host write operations to the TX Data FIFO and all host

read operations from the RX Data FIFO . Depending on the addressing mode of the device, this signal is either

directly provided by the host or is strobed as part of the address input.

When used with the Indexed Addressing mode, burst read access is supported by toggling the lower address bits.

9.2

Read / Write Control Signals

The device supports two distinct read / write signal methods:

• read (RD) and write (WR) strobes are input on separate pins.

• read and write signals are decoded from an enable input (ENB) and a direction input (RD_WR).

9.3

Control Line Polarity

The device supports polarity control on the following:

• chip select input (CS)

• read strobe (RD) / direction input (RD_WR)

• write strobe (WR) / enable input (ENB)

• address latch control (ALELO and ALEHI)

9.4

Multiplexed Address / Data Mode

In Multiplexed Address / Data mode, the address, FIFO Direct Select and endianness select inputs are shared with the

data bus. Two methods are supported, a single phase address, utilizing up to 16 address / data pins and a dual phase

address, utilizing only the lower 8 data bits.

9.4.1

ADDRESS LATCH CYCLES

9.4.1.1

Single Phase Address Latching

In Single Phase mode, all address bits, the FIFO Direct Select signal and the endianness select are strobed into the

device using the trailing edge of the ALELO signal. The address latch is implemented on all 16 address / data pins. In

8-bit data mode, where pins AD[15:8] are used exclusively for addressing, it is not necessary to drive these upper

address lines with a valid address continually through read and write operations. However, this operation, referred to as

Partial Address Multiplexing, is acceptable since the device will never drive these pins.

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