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LAN9250 Datasheet(PDF) 18 Page - Microchip Technology |
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LAN9250 Datasheet(HTML) 18 Page - Microchip Technology |
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18 / 421 page  LAN9250 DS00001913A-page 18 2015 Microchip Technology Inc. 1 FX Signal Detect (SD) FXSDA ILVPECL Fiber Signal Detect. When FX-LOS mode is not selected, this pin functions as the Signal Detect input from the external transceiver. A level above 2 V (typ.) indicates valid signal. When FX-LOS mode is selected, the input buffer is disabled. FX Loss Of Signal (LOS) FXLOSA IS (PU) Fiber Loss of Signal. When FX-LOS mode is selected (via fx_los_strap_1), this pin functions as the Loss of Signal input from the external trans- ceiver. A high indicates LOS while a low indicates valid signal. When FX-LOS mode is not selected, the input buffer and pull-up are disabled. FX-SD Enable Strap FXSDENA AI FX-SD Enable. When FX-LOS mode is not selected, this strap input selects between FX-SD and copper twisted pair mode. A level above 1 V (typ.) selects FX-SD. When FX-LOS mode is selected, the input buffer is disabled. See Note 2. 1 Bias Reference RBIAS AI Used for internal bias circuits. Connect to an exter- nal 12.1 kΩ, 1% resistor to ground. Refer to the device reference schematic for connec- tion information. Note: The nominal voltage is 1.2 V and the resistor will dissipate approximately 1 mW of power. 1 FX-LOS Enable Strap FXLOSEN AI FX-LOS Enable. This strap input selects between FX-LOS and FX-SD / copper twisted pair mode. A level below 1 V (typ.) selects FX-SD / copper twisted pair for the port, further determined by FXS- DENA. A level of 1.5 V (typ.) or above selects FX-LOS for the port. See Note 2. 1 +3.3 V Analog Power Supply VDD33TXRX1 P See Note 3. 1 +3.3 V Analog Power Supply VDD33TXRX2 P See Note 3. 1 +3.3 V Master Bias Power Supply VDD33BIAS P See Note 3. TABLE 3-3: LAN PIN DESCRIPTIONS (CONTINUED) Num Pins Name Symbol Buffer Type Description |
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