LAN9250 datasheet(20/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 20

 2015 Microchip Technology Inc.

Chip Select

VIS

This pin is the host bus chip select and indicates

that the device is selected for the current transfer.

Normally active low, the polarity can be changed via

the HBI_cs_polarity_strap.

FIFO Select

FIFOSEL

VIS

This input directly selects the Host MAC TX and RX

Data FIFOs for non-multiplexed address mode.

5Address

A[4:0]

VIS

These pins provide the address for non-multiplexed

address mode.

In 16-bit data mode, bit 0 is not used.

Data

D[15:0]

VIS/VO8

These pins are the host bus data bus for non-multi-

plexed address mode.

In 8-bit data mode, bits 15-8 are not used and their

input and output drivers are disabled.

Address & Data

AD[15:0]

VIS/VO8

These pins are the host bus address / data bus for

multiplexed address mode.

Bits 15-8 provide the upper byte of address for sin-

gle phase multiplexed address mode.

Bits 7-0 provide the lower byte of address for single

phase multiplexed address mode and both bytes of

address for dual phase multiplexed address mode.

In 8-bit data dual phase multiplexed address mode,

bits 15-8 are not used and their input and output

drivers are disabled.

Address Latch

Enable High

ALEHI

VIS

This pin indicates the address phase for multiplexed

address modes. It is used to load the higher

address byte in dual phase multiplexed address

mode.

Normally active low (address saved on rising edge),

the polarity can be changed via the HBI_ale_polari-

ty_strap.

Address Latch

Enable Low

ALELO

VIS

This pin indicates the address phase for multiplexed

address modes. It is used to load both address

bytes in single phase multiplexed address mode

and the lower address byte in dual phase multi-

plexed address mode.

Normally active low (address saved on rising edge),

the polarity can be changed via the HBI_ale_polari-

ty_strap.

TABLE 3-4:

HOST BUS PIN DESCRIPTIONS (CONTINUED)

Num

Pins

Name

Symbol

Buffer

Type

Description

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