LAN9250 datasheet(80/421 Pages) MICROCHIP

80 / 421 page

LAN9250

DS00001913A-page 80

 2015 Microchip Technology Inc.

9.4.3

TX AND RX FIFO ACCESS

9.4.3.1

TX and RX Status FIFO Peek Address Access

Normal read access to the TX or RX Status FIFO causes the FIFO to advance to its next entry.

For access to the TX and RX Status FIFO Peek addresses, the FIFO does not advance to its next entry.

9.4.3.2

FIFO Direct Select Access

A FIFO Direct Select signal is provided allows the host system to address the TX and RX Data FIFOs as if they were a

large flat address space. When the FIFO Direct Select signal, which was latched during the address latch cycle, is active

all host write operations are to the TX Data FIFO and all host read operations are from the RX Data FIFO. Only the lower

latched address signals are decoded in order to select the proper BYTE or WORD. All other address inputs are ignored

in this mode. All other operations are the same (DWORD assembly, FIFO popping, etc.).

The endianness of FIFO Direct Select accesses is determined by the endianness select that was latched during the

address latch cycle.

Burst access when reading the RX Data FIFO is not supported. However, since the FIFO Direct Select signal is retained

until either a reset event occurs or a new address is loaded, multiple read or write requests can occur without requiring

multiple address latching operations.

9.4.4

MULTIPLEXED ADDRESSING MODE FUNCTIONAL TIMING DIAGRAMS

The following timing diagrams illustrate example multiplexed addressing mode read and write cycles for various

address/data configurations and bus sizes. These diagrams do not cover every supported host bus permutation, but are

selected to detail the main configuration differences (bus size, dual/single phase address latching) within the multiplexed

addressing mode of operation.

The following should be noted for the timing diagrams in this section:

• The diagrams in this section depict active-high ALEHI/ALELO, CS, RD, and WR signals. The polarities of these

signals are selectable via the HBI_ale_polarity_strap, HBI_cs_polarity_strap, HBI_rd_rdwr_polarity_strap, and

HBI_wr_en_polarity_strap, respectively. Refer to Section 9.3, "Control Line Polarity," on page 74 for additional

details.

• The diagrams in this section depict little endian byte ordering. However, dynamic big and little endianess are sup-

ported via the endianess signal. Endianess changes only the order of the bytes involved, and not the overall tim-

ing requirements. Refer to Section 9.4.1.4, "Endianness Select to Address / Data Pin Mapping," on page 75 for

additional information.

• The diagrams in Section 9.4.4.1, "Dual Phase Address Latching" and Section 9.4.4.2, "Single Phase Address

Latching" utilize RD and WR signals. Alternative RD_WR and ENB signaling is also supported, as shown in Sec-

tion 9.4.4.3, "RD_WR / ENB Control Mode Examples". The HBI read/write mode is selectable via the HBI_rw_-

mode_strap. The polarities of the RD_WR and ENB signals are selectable via the HBI_rd_rdwr_polarity_strap,

and HBI_wr_en_polarity_strap.

• Qualification of the ALELO and/or ALEHI with the CS signal is selectable via the HBI_ale_qualification_strap.

Refer to Section 9.4.1.1, "Single Phase Address Latching," on page 74 and Section 9.4.1.2, "Dual Phase Address

Latching," on page 75 for additional information.

• In dual phase address latching mode, the ALEHI and ALELO cycles can be in any order. Either or both ALELO

and ALEHI cycles maybe skipped and the device retains the last latched address.

• In single phase address latching mode, the ALELO cycle maybe skipped and the device retains the last latched

address.

• For 16 and 8-bit modes, consecutive address cycles must be within the same DWORD until the DWORD is com-

pletely accessed (with the register exceptions noted above). Although BYTEs and WORDs can be accessed in

any order, the diagrams in this section depict accessing the lower address BYTE or WORD first.

Note:

In 8 and 16-bit modes, the ALELO cycle is normally not skipped since sequential BYTEs or WORDs are

accessed in order to satisfy a complete DWORD cycle. However, there are registers for which a single

BYTE or WORD access is allowed, in which case multiple accesses to these registers may be performed

without the need to re-latch the repeated address.

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