LAN9250 datasheet(31/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 31

LAN9250

5.1

System Control and Status Registers

The System CSRs are directly addressable memory mapped registers with a base address offset range of 050h to 1F8h.

These registers are addressable by the Host via the Host Bus Interface (HBI) or SPI/SQI. For more information on the

various device modes and their corresponding address configurations, see Section 2.0, "General Description," on

page 8.

Table 5-1 lists the System CSRs and their corresponding addresses in order. All system CSRs are reset to their default

value on the assertion of a chip-level reset.

The System CSRs can be divided into the following sub-categories. Each of these sub-categories is located in the cor-

responding chapter and contains the System CSR descriptions of the associated registers. The register descriptions

are categorized as follows:

• Section 6.2.3, "Reset Registers," on page 42

• Section 6.3.5, "Power Management Registers," on page 49

• Section 8.3, "Interrupt Registers," on page 65

• Section 11.14, "Host MAC & FIFO Interface Registers," on page 176

• Section 16.4, "GPIO/LED Registers," on page 386

• Section 13.5, "I2C Master EEPROM Controller Registers," on page 294

• Section 14.8, "1588 Registers," on page 316

• Section 17.1, "Miscellaneous System Configuration & Status Registers," on page 392

Note:

Unlisted registers are reserved for future use.

TABLE 5-1:

SYSTEM CONTROL AND STATUS REGISTERS

Address

000h - 04Ch TX/RX FIFOs

050h

Chip ID and Revision (ID_REV)

054h

Interrupt Configuration Register (IRQ_CFG)

058h

Interrupt Status Register (INT_STS)

05Ch

Interrupt Enable Register (INT_EN)

064h

Byte Order Test Register (BYTE_TEST)

068h

FIFO Level Interrupt Register (FIFO_INT)

06Ch

Receive Configuration Register (RX_CFG)

070h

Transmit Configuration Register (TX_CFG)

074h

Hardware Configuration Register (HW_CFG)

078h

Receive Datapath Control Register (RX_DP_CTRL)

07Ch

RX FIFO Information Register (RX_FIFO_INF)

080h

TX FIFO Information Register (TX_FIFO_INF)

084h

Power Management Control Register (PMT_CTRL)

08Ch

General Purpose Timer Configuration Register (GPT_CFG)

090h

General Purpose Timer Count Register (GPT_CNT)

09Ch

Free Running 25MHz Counter Register (FREE_RUN)

0A0h

Host MAC RX Dropped Frames Counter Register (RX_DROP)

0A4h

Host MAC CSR Interface Command Register (MAC_CSR_CMD)

0A8h

Host MAC CSR Interface Data Register (MAC_CSR_DATA)

0ACh

Host MAC Automatic Flow Control Configuration Register (AFC_CFG)

0B0h

Host MAC RX LPI Transitions Register (HMAC_RX_LPI_TRANSITION)

0B4h

Host MAC RX LPI Time Register (HMAC_RX_LPI_TIME)

0B8h

Host MAC TX LPI Transitions Register (HMAC_TX_LPI_TRANSITION)

0BCh

Host MAC TX LPI Time Register (HMAC_TX_LPI_TIME)

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