LAN9250 datasheet(48/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 48

 2015 Microchip Technology Inc.

6.3.4.1

Entering Low Power Modes

To enter any of the low power modes (D1 - D3) from normal mode (D0), follow these steps:

Write the PM_MODE and PM_WAKE fields in the Power Management Control Register (PMT_CTRL) to their

desired values

Set the wake-up detection desired per Section 6.3.1, "Wake-Up Event Detection".

Set the appropriate wake-up notification per Section 6.3.2, "Wake-Up (PME) Notification".

Ensure that the device is in a state where it can safely be placed into a low power mode (all packets transmitted,

receivers disabled, packets processed / flushed, etc.)

Set the PM_SLEEP_EN bit in the Power Management Control Register (PMT_CTRL).

Note:

The EEPROM Loader Register Data burst sequence (Section 13.4.5) can be used to achieve an initial

power down state without the need of software by:

•First setting the PHY into General Purpose Power Down by

setting the PHY_PWR_DWN bit in PHY_BASIC_CONTROL

indirectly via the HMAC_MII_DATA / HMAC_MII_ACC via the MAC_CSR_CMD / MAC_CSR_DATA reg-

isters.

•Setting the PM_MODE and PM_SLEEP_EN bits in the Power Management Control Register (PMT_C-

TRL).

Upon entering any low power mode, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG)

and the Power Management Control Register (PMT_CTRL) is forced low.

6.3.4.2

Exiting Low Power Modes

Exiting from a low power mode can be done manually or automatically.

An automatic wake-up will occur based on the events described in Section 6.3.2, "Wake-Up (PME) Notification". Auto-

matic wake-up is enabled with the Power Management Wakeup (PM_WAKE) bit in the Power Management Control

A manual wake-up is initiated by the host when:

• an HBI write (CS and WR or CS, RD_WR and ENB) is performed to the device. Although all writes are ignored

until the device has been woken and a read performed, the host should direct the write to the Byte Order Test

• an SPI/SQI cycle (SCS# low and SCK high) is performed to the device. Although all reads and writes are ignored

until the device has been woken, the host should direct the use a read of the Byte Order Test Register

(BYTE_TEST) to wake the device. Reads and writes to any other addresses should not be attempted until the

device is awake.

TABLE 6-2:

POWER MANAGEMENT STATES

Clock Source

25 MHz Crystal Oscillator

OFF

PLL

ONONOFF(2)OFF

system clocks (100 MHz, 50 MHz, 25 MHz and others)

OFF

network clocks

available(1)

available(1)OFF(3)

Note

If supplied by the PHY

PLL is requested to be turned off and will disable if the PHY is in either Energy Detect or General Power Down

PHY clocks are off

Note:

The PM_MODE field cannot be changed at the same time as the PM_SLEEP_EN bit is set and the

PM_SLEEP_EN bit cannot be set at the same time that the PM_MODE field is changed.

Note:

Upon entry into any of the power saving states the host interfaces are not functional.

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