LAN9250 datasheet(72/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 72

 2015 Microchip Technology Inc.

8.3.3

INTERRUPT ENABLE REGISTER (INT_EN)

This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables the corresponding

interrupt as a source for IRQ. Bits in the Interrupt Status Register (INT_STS) register will still reflect the status of the

interrupt source regardless of whether the source is enabled as an interrupt in this register (with the exception of Soft-

ware Interrupt Enable (SW_INT_EN). For descriptions of each interrupt, refer to the Interrupt Status Register (INT_STS)

bits, which mimic the layout of this register.

Offset:

05Ch

Size:

32 bits

Bits

Description

Type

Default

Software Interrupt Enable (SW_INT_EN)

R/W

Device Ready Enable (READY_EN)

R/W

1588 Interrupt Event Enable (1588_EVNT_EN)

R/W

28:27

RESERVED

PHY Interrupt Event Enable (PHY_INT_EN)

R/W

TX Stopped Interrupt Enable (TXSTOP_INT_EN)

R/W

RX Stopped Interrupt Enable (RXSTOP_INT_EN)

R/W

RX Dropped Frame Counter Halfway Interrupt Enable

(RXDFH_INT_EN)

R/W

RESERVED

TX IOC Interrupt Enable (TIOC_INT_EN)

R/W

RX DMA Interrupt Enable (RXD_INT_EN)

R/W

GP Timer Interrupt Enable (GPT_INT_EN)

R/W

RESERVED

Power Management Event Interrupt Enable (PME_INT_EN)

R/W

TX Status FIFO Overflow Interrupt Enable (TXSO_EN)

R/W

Receive Watchdog Time-out Interrupt Enable (RWT_INT_EN)

R/W

Receiver Error Interrupt Enable (RXE_INT_EN)

R/W

Transmitter Error Interrupt Enable (TXE_INT_EN)

R/W

GPIO Interrupt Event Enable (GPIO_EN)

R/W

RESERVED

TX Data FIFO Overrun Interrupt Enable (TDFO_EN)

R/W

TX Data FIFO Available Interrupt Enable (TDFA_EN)

R/W

TX Status FIFO Full Interrupt Enable (TSFF_EN)

R/W

TX Status FIFO Level Interrupt Enable (TSFL_EN)

R/W

RX Dropped Frame Interrupt Enable (RXDF_INT_EN)

R/W

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