LAN9250 datasheet(63/421 Pages) MICROCHIP

63 / 421 page

 2015 Microchip Technology Inc.

DS00001913A-page 63

LAN9250

The following sections detail each category of interrupts and their related registers. Refer to the corresponding function’s

chapter for bit-level definitions of all interrupt registers.

8.2.1

1588 INTERRUPTS

Multiple 1588 Time Stamp interrupt sources are provided by the device. The top-level 1588 Interrupt Event

(1588_EVNT) bit of the Interrupt Status Register (INT_STS) provides indication that a 1588 interrupt event occurred in

the 1588 Interrupt Status Register (1588_INT_STS).

The 1588 Interrupt Enable Register (1588_INT_EN) provides enabling/disabling of all 1588 interrupt conditions. The

1588 Interrupt Status Register (1588_INT_STS) provides the status of all 1588 interrupts. These include TX/RX 1588

clock capture indication, 1588 clock capture for GPIO events, as well as 1588 timer interrupt indication.

In order for a 1588 interrupt event to trigger the external IRQ interrupt pin, the desired 1588 interrupt event must be

enabled in the 1588 Interrupt Enable Register (1588_INT_EN), bit 29 (1588_EVNT_EN) of the Interrupt Enable Register

(INT_EN) must be set and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the of the Interrupt Con-

figuration Register (IRQ_CFG).

For additional details on the 1588 Time Stamp interrupts, refer to Section 14.0, "IEEE 1588," on page 298.

8.2.2

ETHERNET PHY INTERRUPTS

The top-level PHY Interrupt Event (PHY_INT) bit of the Interrupt Status Register (INT_STS) provides indication that a

PHY interrupt event occurred in the PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE).

PHY interrupts are enabled/disabled via their respective PHY Interrupt Mask Register (PHY_INTERRUPT_MASK). The

source of a PHY interrupt can be determined and cleared via the PHY Interrupt Source Flags Register (PHY_INTER-

RUPT_SOURCE). Unique interrupts are generated based on the following events:

• ENERGYON Activated

• Auto-Negotiation Complete

• Remote Fault Detected

• Link Down (Link Status Negated)

FIGURE 8-1:

FUNCTIONAL INTERRUPT HIERARCHY

INT_CFG

INT_STS

INT_EN

Top Level Interrupt Registers

(System CSRs)

Bit 29 (1588_EVNT)

of INT_STS register

PHY_INTERRUPT_SOURCE

PHY_INTERRUPT_MASK

PHY Interrupt Registers

Bit 26 (PHY_INT)

of INT_STS register

PMT_CTRL

Power Management Control Register

Bit 17 (PME_INT)

of INT_STS register

GPIO_INT_STS_EN

GPIO Interrupt Register

Bit 12 (GPIO)

of INT_STS register

1588_INT_STS

1588_INT_EN

1588 Time Stamp Interrupt Registers

LAN9250 Datasheet(PDF) 63 Page - Microchip Technology

LAN9250 Datasheet(HTML) 63 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL