LAN9250 datasheet(69/421 Pages) MICROCHIP

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DS00001913A-page 69

LAN9250

8.3.2

INTERRUPT STATUS REGISTER (INT_STS)

This register contains the current status of the generated interrupts. A value of 1 indicates the corresponding interrupt

conditions have been met, while a value of 0 indicates the interrupt conditions have not been met. The bits of this register

reflect the status of the interrupt source regardless of whether the source has been enabled as an interrupt in the Inter-

rupt Enable Register (INT_EN). Where indicated as R/WC, writing a 1 to the corresponding bits acknowledges and

clears the interrupt.

Offset:

058h

Size:

32 bits

Bits

Description

Type

Default

Software Interrupt (SW_INT)

This interrupt is generated when the Software Interrupt Enable

(SW_INT_EN) bit of the Interrupt Enable Register (INT_EN) is set high.

Writing a one clears this interrupt.

R/WC

Device Ready (READY)

This interrupt indicates that the device is ready to be accessed after a

power-up or reset condition.

R/WC

1588 Interrupt Event (1588_EVNT)

This bit indicates an interrupt event from the IEEE 1588 module. This bit

should be used in conjunction with the 1588 Interrupt Status Register

(1588_INT_STS) to determine the source of the interrupt event within the

1588 module.

RESERVED

PHY Interrupt Event (PHY_INT)

This bit indicates an interrupt event from PHY. The source of the interrupt

can be determined by polling the PHY Interrupt Source Flags Register

(PHY_INTERRUPT_SOURCE).

TX Stopped (TXSTOP_INT)

This interrupt is issued when the Stop Transmitter (STOP_TX) bit in Trans-

mit Configuration Register (TX_CFG) is set and the Host MAC transmitter is

halted.

R/WC

RX Stopped (RXSTOP_INT)

his interrupt is issued when the Receiver Enable (RXEN) bit in Host MAC

Control Register (HMAC_CR) is cleared and the Host MAC receiver is

halted.

R/WC

RX Dropped Frame Counter Halfway (RXDFH_INT)

This interrupt is issued when the Host MAC RX Dropped Frames Counter

80000000h).

R/WC

RESERVED

TX IOC Interrupt (TX_IOC)

This interrupt is generated when a buffer with the IOC flag set has been fully

loaded into the TX Data FIFO.

R/WC

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