LAN9250 datasheet(70/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 70

 2015 Microchip Technology Inc.

RX DMA Interrupt (RXD_INT)

This interrupt is issued when the amount of data programmed in the RX

DMA Count (RX_DMA_CNT) field of the Receive Configuration Register

(RX_CFG) has been transferred out of the RX Data FIFO.

R/WC

GP Timer (GPT_INT)

This interrupt is issued when the General Purpose Timer Count Register

(GPT_CNT) wraps past zero to FFFFh.

R/WC

RESERVED

Power Management Interrupt Event (PME_INT)

This interrupt is issued when a Power Management Event is detected as

configured in the Power Management Control Register (PMT_CTRL). This

interrupt functions independent of the PME signal and will still function if the

PME signal is disabled. Writing a '1' clears this bit regardless of the state of

the PME hardware signal. In order to clear this bit, all unmasked bits in the

Power Management Control Register (PMT_CTRL) must first be cleared.

Note:

The Interrupt De-assertion interval does not apply to the PME

interrupt.

R/WC

TX Status FIFO Overflow (TXSO)

This interrupt is generated when the TX Status FIFO overflows.

R/WC

Receive Watchdog Time-out (RWT)

This interrupt is generated when a frame greater than or equal to 2048 bytes

has been received by the Host MAC. Frames greater than or equal to 2049

bytes are truncated to 2048 bytes.

R/WC

Receiver Error (RXE)

Indicates that the Host MAC receiver has encountered an error. Please refer

to Section 11.12.5, "Receiver Errors," on page 174 for a description of the

conditions that will cause an RXE.

R/WC

Transmitter Error (TXE)

When generated, indicates that the Host MAC transmitter has encountered

an error. Please refer to Section 11.11.7, "Transmitter Errors," on page 170

for a description of the conditions that will cause a TXE.

R/WC

GPIO Interrupt Event (GPIO)

This bit indicates an interrupt event from the General Purpose I/O. The

source of the interrupt can be determined by polling the General Purpose I/

O Interrupt Status and Enable Register (GPIO_INT_STS_EN)

RESERVED

TX Data FIFO Overrun Interrupt (TDFO)

This interrupt is generated when the TX Data FIFO is full and another write

is attempted.

R/WC

TX Data FIFO Available Interrupt (TDFA)

This interrupt is generated when the TX Data FIFO available space is

greater than the programmed level in the TX Data Available Level field of

the FIFO Level Interrupt Register (FIFO_INT).

R/WC

TX Status FIFO Full Interrupt (TSFF)

This interrupt is generated when the TX Status FIFO is full.

R/WC

Bits

Description

Type

Default

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