LAN9250 datasheet(29/421 Pages) MICROCHIP

29 / 421 page

 2015 Microchip Technology Inc.

DS00001913A-page 29

LAN9250

5.0

This chapter details the device register map and summarizes the various directly addressable System Control and Sta-

tus Registers (CSRs). Detailed descriptions of the System CSRs are provided in the chapters corresponding to their

function. Additional indirectly addressable registers are available in the various sub-blocks of the device. These regis-

ters are also detailed in their corresponding chapters.

Directly Addressable Registers

• Section 11.10.1, "TX/RX FIFOs," on page 157

• Section 5.1, "System Control and Status Registers," on page 31

Indirectly Addressable Registers

• Section 11.15, "Host MAC Control and Status Registers," on page 192

• Section 12.2.18, "PHY Registers," on page 230

Figure 5-1 contains an overall base register memory map of the device. This memory map is not drawn to scale, and

should be used for general reference only. Table 5-1 provides a summary of all directly addressable CSRs and their

corresponding addresses.

Note:

Not all device registers are memory mapped or directly addressable. For details on the accessibility of the

various device registers, refer the register sub-sections listed above.

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