LAN9250 datasheet(44/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 44

 2015 Microchip Technology Inc.

6.3

Power Management

The device supports several block and chip level power management features as well as wake-up event detection and

notification.

6.3.1

WAKE-UP EVENT DETECTION

6.3.1.1

Host MAC Wake on LAN (WoL)

The Host MAC provides the following Wake-on-LAN detection modes:

Perfect DA (Destination Address)

: This mode, enabled by the Perfect DA Wakeup Enable (PFDA_EN) bit in

the Host MAC Wake-up Control and Status Register (HMAC_WUCSR), will trigger a WoL event when an incom-

ing frame has a destination address field that exactly matches the MAC address programmed into the MAC. The

Perfect DA Frame Received (PFDA_FR) bit in the Host MAC Wake-up Control and Status Register

(HMAC_WUCSR) will be set when PFDA_EN is set, and a Perfect DA event occurs.

Broadcast

: This mode, enabled by the Broadcast Wakeup Enable (BCST_EN) bit in the Host MAC Wake-up

Control and Status Register (HMAC_WUCSR), will trigger a WoL event when an incoming frame is a broadcast

frame. The Broadcast Frame Received (BCAST_FR) bit in the Host MAC Wake-up Control and Status Register

(HMAC_WUCSR) will be set when BCST_EN is set, and a Broadcast event occurs.

Remote Wake-up Frame

: This mode, enabled by the Wake-Up Frame Enable (WUEN) bit in the Host MAC

Wake-up Control and Status Register (HMAC_WUCSR), will trigger a WoL event when an incoming frame is

accepted based on the Wake-Up Filter registers in the Host MAC. The Remote Wake-Up Frame Received

(WUFR) bit in the Host MAC Wake-up Control and Status Register (HMAC_WUCSR) will be set when WUEN is

set, and a Remove Wake-up Frame event occurs.

Magic Packet

: This mode, enabled by the Magic Packet Enable (MPEN) bit in the Host MAC Wake-up Control

and Status Register (HMAC_WUCSR), will trigger a WoL event when an incoming frame is accepted and is a

Magic Packet. The Magic Packet Received (MPR) bit in the Host MAC Wake-up Control and Status Register

(HMAC_WUCSR) will be set when MPEN is set, and a Magic Packet event occurs.

If any of the PFDA_FR, BCAST_FR, WUFR or MPR bits are set, the Wake On Status (WOL_STS) bit of the Power Man-

agement Control Register (PMT_CTRL) will be set. The Wake-On-Enable (WOL_EN) enables this bit as a PME event.

In addition, when the Power Management Wakeup (PM_WAKE) bit in the Power Management Control Register

(PMT_CTRL) is set, these events can wake up the chip.

Refer to Section 11.6.1, "Perfect DA Detection," on page 144, Section 11.6.2, "Broadcast Detection," on page 145, Sec-

tion 11.6.3, "Wake-up Frame Detection," on page 145 and Section 11.6.4, "Magic Packet Detection," on page 150 for

additional details on these features.

6.3.1.2

PHY Energy Detect

Energy Detect Power Down mode reduces PHY power consumption. In energy-detect power-down mode, the PHY will

resume from power-down when energy is seen on the cable (typically from link pulses) and set the ENERGYON inter-

rupt bit in the PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE).

Refer to Section 12.2.10.2, "Energy Detect Power-Down," on page 223 for details on the operation and configuration of

the PHY energy-detect power-down mode.

If enabled, via the PHY Interrupt Mask Register (PHY_INTERRUPT_MASK), the PHY will generate an interrupt. This

interrupt is reflected in the Interrupt Status Register (INT_STS), bit 26 (PHY_INT). The INT_STS register bit will trigger

the IRQ interrupt output pin if enabled, as described in Section 8.2.2, "Ethernet PHY Interrupts," on page 63.

The energy-detect PHY interrupt will also set the Energy-Detect Status (ED_STS) bit of the Power Management Con-

trol Register (PMT_CTRL). The Energy-Detect Enable (ED_EN) bit will enable the status bit as a PME event.

Note:

If a carrier is present when Energy Detect Power Down is enabled, then detection will occur immediately.

Note:

Any PHY interrupt will set the above status bits. The Host should only enable the appropriate PHY interrupt

source in the PHY Interrupt Mask Register (PHY_INTERRUPT_MASK).

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