LAN9250 datasheet(117/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 117

LAN9250

9.5.7.2

FIFO Direct Select Burst Timing Requirements

If RD and WR signaling is used, a host burst read from the FIFO begins when RD is asserted with CS active and FIFO-

SEL high. As the address changes, the next data is read. The cycle ends when RD is de-asserted. CS maybe asserted

and de-asserted along with RD but not during RD active.

Alternatively, if RD_WR and ENB signaling is used, a host burst read from the FIFO begins when ENB is asserted with

CS active, RD_WR indicating a read and FIFOSEL high. As the address changes, the next data is read. The cycle ends

when ENB is de-asserted. CS maybe asserted and de-asserted along with ENB but not during ENB active.

Please refer to Section 9.5.6, "Indexed Address Mode Functional Timing Diagrams," on page 102 for functional descrip-

tions.

FIGURE 9-43:

INDEXED ADDRESSING FIFO DIRECT SELECT BURST READ CYCLE TIMING

TABLE 9-5:

INDEXED ADDRESSING FIFO DIRECT SELECT BURST READ CYCLE TIMING

VALUES

Symbol

Description

Min

Typ

Max

Units

tcsrd

CS Setup to RD or ENB Active

trdcs

CS Hold from RD or ENB Inactive

tas

Address, FIFOSEL Setup to RD or ENB Active

tah

Address, FIFOSEL Hold from to RD or ENB Inactive

trdwrs

RD_WR Setup to ENB Active

Note 16

5ns

trdwrh

RD_WR Hold from ENB Inactive

Note 16

5ns

trdon

RD or ENB to Data Buffer Turn On

trddv

RD or ENB Active to Data Valid

trddh

Data Output Hold Time from RD or ENB Inactive

trddz

Data Buffer Turn Off Time from RD or ENB Inactive

FIFOSEL

A[4:0]

ENB, RD

D[15:8]

D[7:0]

trddh, tcsdh

tfdv

trddz, tcsdz

trdrd

trdwr

RD_WR

trdwrs

trdwrh

tcsrd

trdcs

tas

tah

tas

tah

tacyc

tadv

tacyc

tadv

trddv, tcsdv

trdon, tcson

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