LAN9250 datasheet(177/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 177

LAN9250

11.14.1

FIFO LEVEL INTERRUPT REGISTER (FIFO_INT)

This read/write register configures the limits where the RX/TX Data and Status FIFO’s will generate system interrupts.

Offset:

068h

Size:

32 bits

Bits

Description

Type

Default

31:24

TX Data Available Level

The value in this field sets the level, in number of 64 Byte blocks, at which the

TX Data FIFO Available Interrupt (TDFA) will be generated. When the TX

Data FIFO free space is greater than this value, a TX Data FIFO Available

Interrupt (TDFA) will be generated in the Interrupt Status Register (INT_STS).

R/W

48h

23:16

TX Status Level

The value in this field sets the level, in number of DWORDs, at which the TX

Status FIFO Level Interrupt (TSFL) will be generated. When the TX Status

FIFO used space is greater than this value, a TX Status FIFO Level Interrupt

(TSFL) will be generated in the Interrupt Status Register (INT_STS).

R/W

00h

15:8

RESERVED

7:0

RX Status Level

The value in this field sets the level, in number of DWORDs, at which the RX

Status FIFO Level Interrupt (RSFL) will be generated. When the RX Status

FIFO used space is greater than this value, a RX Status FIFO Level Interrupt

(RSFL) will be generated in the Interrupt Status Register (INT_STS).

R/W

00h

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