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DS26401 Datasheet(PDF) 201 Page - Dallas Semiconductor |
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DS26401 Datasheet(HTML) 201 Page - Dallas Semiconductor |
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201 / 309 page  DS26401 Octal T1/E1/J1 Framer 201 10.16.1 HDLC FIFO Control Control of the receive FIFO is accomplished via the Receive HDLC FIFO Control (RHFC). The FIFO Control register sets the watermarks for the receive FIFO. When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) will be set. RHWM is a real-time bit and will remain set as long as the receive FIFO’s write pointer is above the watermark. If enabled, this condition can also cause an interrupt via the INT pin. Register Name: RHFC Register Description: Receive HDLC FIFO Control Register Register Address: 087h + (200h x n) : where n = 0 to 7, for Ports 1 to 8 Bit # 7 6 5 4 3 2 1 0 Name — — — — — — RFHWM1 RFHWM0 Default 0 0 0 0 0 0 0 0 Bits 0 to 1 / Receive FIFO High Watermark Select (RFHWM0 to RFHWM1) RFHWM1 RFHWM0 Receive FIFO Watermark (bytes) 0 0 4 0 1 16 1 0 32 1 1 48 Bits 2 to 7/ Unused. Must be set = 0 for proper operation. |
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