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DS26401 Datasheet(PDF) 247 Page - Dallas Semiconductor

Part # DS26401
Description  Octal T1/E1/J1 Framer
PDF  309 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS26401 Datasheet(HTML) 247 Page - Dallas Semiconductor

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DS26401 Octal T1/E1/J1 Framer
247
11.17 Transmit HDLC Controller
Each framer port has an HDLC controller with 64-byte FIFOs.
The HDLC controller can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 mode).
This block has 64 byte FIFO buffers in both the transmit and receive paths. The user can select any specific bits
within the time slot(s) to assign to the HDLC controller, as well as specific Sa bits (E1 mode). The HDLC controllers
automatically generate and detect flags, generate and check the CRC checksum, generate and detect abort
sequences, stuff and destuff zeros, and byte align to the data stream.



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