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TDA2EX Datasheet(PDF) 127 Page - Texas Instruments |
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TDA2EX Datasheet(HTML) 127 Page - Texas Instruments |
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127 / 391 page  127 TDA2EG-17 www.ti.com SPRS969B – AUGUST 2016 – REVISED JUNE 2017 Submit Documentation Feedback Product Folder Links: TDA2EG-17 Specifications Copyright © 2016–2017, Texas Instruments Incorporated Table 5-6. LVCMOS DDR DC Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT Single-Ended Receiver Mode VIH High-level input threshold DDR3/DDR3L VREF+0.1 VDDS+0.2 V VIL Low-level input threshold DDR3/DDR3L -0.2 VREF-0.1 V VCM Input common-mode voltage VREF -10%vdds VREF+ 10%vdds V CPAD Pad capacitance (including package capacitance) 3 pF Differential Receiver Mode VSWING Input voltage swing DDR3/DDR3L 0.2 vdds+0.4 V VCM Input common-mode voltage VREF -10%vdds VREF+ 10%vdds V CPAD Pad capacitance (including package capacitance) 3 pF (1) VDDS in this table stands for corresponding power supply (i.e. vdds_ddr1). For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [10] column. (2) VREF in this table stands for corresponding Reference Power Supply (i.e. ddr1_vref0). For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [10] column. (3) For more information on the I/O cell configurations (i[2:0], sr[1:0]), see the Chapter Control Module of the Device TRM. Table 5-7. Dual Voltage LVCMOS I2C DC Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT Signal Names in MUXMODE 0: i2c1_scl; i2c1_sda; i2c2_scl; i2c_sda; Balls: G22 / G23 / G21 / F23 I2C Standard Mode – 1.8 V VIH Input high-level threshold 0.7 × VDDS V VIL Input low-level threshold 0.3 × VDDS V Vhys Hysteresis 0.1 × VDDS V IIN Input current at each I/O pin with an input voltage between 0.1 × VDDS to 0.9 × VDDS 12 µA IOZ IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ 12 µA CIN Input capacitance 10 pF VOL3 Output low-level threshold open-drain at 3-mA sink current 0.2 × VDDS V IOLmin Low-level output current @VOL=0.2 × VDDS 3 mA tOF Output fall time from VIHmin to VILmax with a bus capacitance CB from 5 pF to 400 pF 250 ns I2C Fast Mode – 1.8 V VIH Input high-level threshold 0.7 × VDDS V VIL Input low-level threshold 0.3 × VDDS V Vhys Hysteresis 0.1 × VDDS V IIN Input current at each I/O pin with an input voltage between 0.1 × VDDS to 0.9 × VDDS 12 µA IOZ IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ 12 µA CIN Input capacitance 10 pF |
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