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TDA2EX Datasheet(PDF) 130 Page - Texas Instruments |
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TDA2EX Datasheet(HTML) 130 Page - Texas Instruments |
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130 / 391 page  130 TDA2EG-17 SPRS969B – AUGUST 2016 – REVISED JUNE 2017 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2EG-17 Specifications Copyright © 2016–2017, Texas Instruments Incorporated Table 5-10. LVCMOS CSI2 DC Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT VIH Input high-level voltage 880 mV VIL Input low-level voltage 300 mV VITH Input high-level threshold 880 mV VITL Input low-level threshold 300 mV VHYS Input hysteresis 25 mV MIPI D-PHY Mode High-Speed Receiver (HS-RX) VIDTH Differential input high-level threshold 70 mV VIDTL Differential input low-level threshold –70 mV VIDMAX Maximum differential input voltage 270 mV VIHHS Single-ended input high voltage 460 mV VILHS Single-ended input low voltage –40 mV VCMRXDC Differential input common-mode voltage 70 330 mV ZID Differential input impedance 80 100 125 Ω (1) VITH is the voltage at which the receiver is required to detect a high state in the input signal. (2) VITL is the voltage at which the receiver is required to detect a low state in the input signal. VITL is larger than the maximum single-ended line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling. (3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, VHYST. VHYST is the difference between the VITH threshold and the VITL threshold. (4) VITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state. (5) Excluding possible additional RF interference of 200 mVPP beyond 450 MHz. (6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and variations below 450 MHz. (7) This number corresponds to the VODMAX transmitter. (8) Common mode is defined as the average voltage level of X and Y: VCMRX = (VX + VY) / 2. (9) Common mode ripple may be due to tR or tF and transmission line impairments in the PCB. (10) For more information regarding the pin name (or ball name) and corresponding signal name, see Table 4-5 CSI 2 Signal Descriptions. Table 5-11. Dual Voltage SDIO1833 DC Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT Signal Names in Mode 0: mmc1_clk, mmc1_cmd, mmc1_data[3:0] Bottom Balls: U3 / V4 / V3 / V2 / W1 / V1 1.8-V Mode VIH Input high-level threshold 1.27 V VIL Input low-level threshold 0.58 V VHYS Input hysteresis voltage 50 (2) mV IIN Input current at each I/O pin 30 µA IOZ IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ 30 µA IIN with pulldown enabled Input current at each I/O pin with weak pulldown enabled measured when PAD = VDDS 50 120 210 µA IIN with pullup enabled Input current at each I/O pin with weak pullup enabled measured when PAD = 0 60 120 200 µA CPAD Pad capacitance (including package capacitance) 5 pF VOH Output high-level threshold (IOH = 2 mA) 1.4 V |
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