DS3141 datasheet(56/88 Pages) DALLAS

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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

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HCR2

HDLC Control Register 2

51h

Bit #

Name

N/A

RHWMS2

RHWMS1

RHWMS0

N/A

TLWMS2

TLWMS1

TLWMS0

Default

—

Bits 2 to 0: Transmit Low Watermark Select Bits (TLWMS[2:0]). These control bits determine when the HDLC

controller should set the TLWM status bit in the HSR register. When the transmit FIFO contains less than the

number of bytes specified by these bits, the TLWM status bit is set to logic 1.

TLWMS[2:0]

TRANSMIT LOW WATERMARK (BYTES)

000

001

010

011

112

100

144

101

176

110

208

111

240

Bits 4 to 6: Receive High Watermark Select Bits (RHWMS[2:0]). These control bits determine when the HDLC

controller should set the RHWM status bit in the HSR register. When the receive FIFO contains more than the

number of bytes specified by these bits, the RHWM status bit is set to logic 1.

RHWMS[2:0]

RECEIVE HIGH WATERMARK (BYTES)

000

001

010

011

112

100

144

101

176

110

208

111

240

HSR

HDLC Status Register

54h

Bit #

Name

N/A

RHWM

TLWM

N/A

Default

—

Bit 2: Transmit FIFO Low Watermark (TLWM). This real-time status bit is set to 1 when the transmit FIFO

contains less than the number of bytes configured by TLWMS[2:0] control bits in the HCR2 register. This bit is

cleared when the FIFO fills beyond the low watermark.

Bit 3: Receive FIFO High Watermark (RHWM). This real-time status bit is set to 1 when the receive FIFO

contains more than the number of bytes configured by the RHWMS[2:0] control bits in the HCR2 register. This bit is

cleared when the FIFO empties below the high watermark.

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