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DS3141 Datasheet(PDF) 43 Page - Dallas Semiconductor |
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DS3141 Datasheet(HTML) 43 Page - Dallas Semiconductor |
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43 / 88 page  DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers 43 of 88 Register Name: FECR1 Register Description: Frame Error Count Register 1 Register Address: 24h Bit # 7 6 5 4 3 2 1 0 Name FE7 FE6 FE5 FE4 FE3 FE2 FE1 FE0 Default 0 0 0 0 0 0 0 0 Register Name: FECR2 Register Description: Frame Error Count Register 2 Register Address: 25h Bit # 7 6 5 4 3 2 1 0 Name FE15 FE14 FE13 FE12 FE11 FE10 FE9 FE8 Default 0 0 0 0 0 0 0 0 Bits 0 to 15: Frame Error Count (FE[15:0]). This count register contains the value of the internal framer error counter latched during the last error counter update. The internal counter counts either the number of OOF occurrences or the number of framing bit errors received. The type of counting is configured through the FECC[1:0] control bits in the T3E3CR2 register. The possible configurations are shown below. FECC[1:0] Frame Error-Count Register (FECR1) Configuration 00 DS3 Mode: Count OOF occurrences E3 Mode: Count OOF occurrences 01 DS3 Mode: Count both F-bit and M-bit errors E3 Mode: Count bit errors in the FAS word 10 DS3 Mode: Count only F-bit errors E3 Mode: Count word errors in the FAS word 11 DS3 Mode: Count only M-bit errors E3 Mode: Illegal state When the counter is configured to count OOF occurrences, it increments by one each time the framer loses receive synchronization. When the counter is configured to count framing bit errors, the counter can be configured through the ECC control bit in the T3E3CR2 register to either continue counting frame bit errors during an OOF event or not. Register Name: PCR1 Register Description: P-Bit Parity Error Count Register 1 Register Address: 26h Bit # 7 6 5 4 3 2 1 0 Name PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Default 0 0 0 0 0 0 0 0 Register Name: PCR2 Register Description: P-Bit Parity Error Count Register 2 Register Address: 27h Bit # 7 6 5 4 3 2 1 0 Name PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 Default 0 0 0 0 0 0 0 0 Bits 0 to 15: P-Bit Parity Error Count (PE[15:0]). This count register contains the value of the internal P-bit parity error counter latched during the last error counter update. The internal counter counts the number of DS3 P-bit parity errors. In E3 mode this counter is meaningless and should be ignored. A P-bit parity error is defined as an occurrence when the two P bits in a DS3 frame do not match one another or when the two P bits do not match the parity calculation made on the information bits. Through the ECC control bit in the T3E3CR2 register, the counter can be configured to either continue counting P-bit parity errors during an OOF event or not. |
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