DS3141 datasheet(53/88 Pages) DALLAS

53 / 88 page

DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

53 of 88

BBECR1

BERT Bit-Error Counter Register 1 (lower byte)

44h

Bit #

Name

BEC7

BEC6

BEC5

BEC4

BEC3

BEC2

BEC1

BEC0

Default

BBECR2

BERT Bit Error Counter Register 2

45h

Bit #

Name

BEC15

BEC14

BEC13

BEC12

BEC11

BEC10

BEC9

BEC8

Default

BBECR3

BERT Bit Error Counter Register 3 (upper byte)

46h

Bit #

Name

BEC23

BEC22

BEC21

BEC20

BEC19

BEC18

BEC17

BEC16

Default

Bits 0 to 23: BERT Bit-Error Counter (BEC[23:0]). The BBECR registers are loaded with the value of the internal

BERT error counter when the LC control bit in the BCR1 register is toggled. This 24-bit counter increments for each

received data bit that does not match the expected pattern. The error counter starts counting when the BERT goes

into receive synchronization (SYNC = 1) and continues counting even if the BERT loses sync. The error counter

saturates and does not roll over. Upon saturation, the BECO status bit in the BSR register is set. When the LC bit is

toggled, the error count is loaded into the BBECR registers and the internal error counter is cleared. If the BERT is

in sync when LC is toggled, the error counter continues to count up from zero. If the BERT is out of sync when LC

is toggled, the error counter is held at zero until the BERT regains sync. The host processor should toggle LC after

the BERT has synchronized and then toggle LC again when the error-checking period is complete. If the framer

loses synchronization during this period, then the counting results are suspect.

7.10 HDLC Controller

Each framer contains an on-board HDLC controller with 256-byte buffers in the transmit and receive paths. When

the framer is operated in the DS3 C-Bit Parity mode, the HDLC transmitter and receiver are connected to the three

C-bits in M-subframe 5. When the framer is operated in the E3 mode, the user has the option to connect the HDLC

transmitter to the Sn bit, while the HDLC receiver is always connected to the Sn bit in the receive data. If the host

processor does not wish to use the HDLC controller for the Sn bit, then the status provided by the HDLC controller

should be ignored. On the transmit side, the host processor selects the source of the Sn bit through the E3SnC0

and E3SnC1 controls bits in the T3E3CR1 register. The HDLC controller is not used in the DS3 M23 mode.

7.10.1 Receive Operation

On reset, the receive HDLC controller flushes the receive FIFO and begins searching for a new incoming HDLC

packet. It then performs a bit-by-bit search for an HDLC packet and when one is detected, it zero destuffs the

incoming data stream, automatically byte aligns to it, and places the incoming bytes into the receive FIFO as they

are received. The first byte of each packet is marked in the receive FIFO by setting the opening byte (OBYTE) bit.

Upon detecting a closing flag, the receive HDLC controller checks the 16-bit CRC to see if the packet is valid or not

and then marks the last byte of the packet in the receive FIFO by setting the closing byte (CBYTE) bit. The CRC is

not passed to the receive FIFO. When the CBYTE bit is set, the host processor can obtain the status of the

incoming packet through the packet status bits (PS0 and PS1). Incoming packets can be separated by as few as

one flag or by two flags that share a common zero. If the receive FIFO ever fills beyond capacity, the rest of the

incoming packet data is discarded, and the receive FIFO overrun (ROVRL) status bit is set. If such a scenario

occurs, then the last packet in the FIFO is suspect and should be discarded. When an overflow occurs, the receive

DS3141 Datasheet(PDF) 53 Page - Dallas Semiconductor

DS3141 Datasheet(HTML) 53 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL