DS3141 datasheet(70/88 Pages) DALLAS

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Figure 9-2. JTAG TAP Controller State Machine

Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the

controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the Select-

IR-SCAN state.

Capture-DR. Data can be parallel loaded into the test data registers selected by the current instruction. If the

instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register

remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or

to the Exit1-DR state if JTMS is high.

Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO and shifts

data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the current

instruction is not placed in the serial path, it maintains its previous state.

Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state,

which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Pause-DR

state.

Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current

instruction retain their previous state. The controller remains in this state while JTMS is low. A rising edge on

JTCLK with JTMS high puts the controller in the Exit2-DR state.

Test-Logic-Reset

Run-Test/Idle

Select

DR-Scan

Capture-DR

Shift-DR

Exit1- DR

Pause-DR

Exit2-DR

Update-DR

Select

IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

DS3141 Datasheet(PDF) 70 Page - Dallas Semiconductor