DS3141 datasheet(24/88 Pages) DALLAS

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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

24 of 88

MC2

Master Configuration Register 2

02h

Bit #

Name

OSTCS

TCCLK

N/A

DLB

LLB

PLB

Default

—

Bit 0: Payload Loopback Enable (PLB). When payload loopback is enabled, the transmit formatter operates from

the receive clock (rather than TICLK) and sources DS3/E3 payload bits from the receive data stream rather than

from the TDAT input pin. Receive data is still available on the RDAT output pin during payload loopback. See

Figure 1-1 for a visual description of this loopback.

0 = disable payload loopback

1 = enable payload loopback

Bit 1: Line Loopback Enable (LLB). Line loopback connects the TPOS, TNEG, and TCLK output pins to the

RPOS, RNEG, and RCLK input pins. When line loopback is enabled, the receive framer continues to process the

incoming receive data stream and present it on the RDAT pin; the output of the transmit formatter is ignored. Line

loopback and diagnostic loopback can be active at the same time to support simultaneous local and far-end

loopbacks. See Figure 1-1 for a visual description of this loopback.

0 = disable line loopback

1 = enable line loopback

Bit 2: Diagnostic Loopback Enable (DLB). When diagnostic loopback is enabled, the receive framer sources

data from the transmit formatter rather than the RCLK, RPOS, and RNEG input pins. Transmit data is sourced prior

to transmit AIS generation, unframed all-ones generation, TCLK/TPOS/TNEG pin inversion, and TPOS/TNEG

force-high logic. This allows the device to transmit AIS or unframed all ones to the far end while locally looping

back the actual transmit data stream, which could be test patterns or other traffic that should not be sent to the far

end. See Figure 1-1 for a visual description of this loopback.

0 = disable diagnostic loopback

1 = enable diagnostic loopback

Bit 6: Transmit Constant Clock Select (TCCLK). When TCCLK is set to logic 1, the device outputs a constant

transmit clock on the TDEN/TGCLK pin instead of a data enable or gapped clock. This bit has precedence over the

TDENMS bit in register MC3. The pin can still be inverted by MC3:TDENI.

0 = the function of the TDEN/TGCLK pin is controlled by TDENMS control bit

1 = the TDEN/TGCLK pin is a constant transmit clock output

Bit 7: One-Second Timer Clock Select (OSTCS). This control bit selects the clock source for the internal one-

second timer.

0 = use RCLK

1 = use TICLK

DS3141 Datasheet(PDF) 24 Page - Dallas Semiconductor

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