DS3141 datasheet(17/88 Pages) DALLAS

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6.1 Status Register Description

There are two types of bits used to build the status and information registers. The real-time status register bit

indicates the state of the corresponding signal at the time it was read. The latched status register bit is set when

the corresponding signal changes state (low-to-high, high-to-low, or both, depending on the bit). The latched status

bit is cleared when written with logic 1 and is not set again until the corresponding signal changes state again.

The following is example host-processor pseudocode that checks to see if the BERT SYNC status has changed:

If ((BSRL and 01h) neq 0) then

// SYNCL bit is set

BSRL = 01h

// Clear SYNCL bit only

If ((BSR and 01h) neq 0) then

// BERT has changed to in sync

–––––

Else

// BERT has changed to out of sync

–––––

There are four suffixes used for status and information register names: SR for real-time status registers, SRL for

latched status registers, SRIE for interrupt-enable registers, and IR for information registers. Latched status bits

have the suffix “L” and interrupt-enable bits have the suffix “IE.” The bits in the SR, SRL, and SRIE registers are

arranged such that related real-time status, latched status, and interrupt-enable bits are located in the same bit

position in neighboring registers. For example, Table 6-B shows that the real-time status bit SYNC, the latched

status bit SYNCL, and the interrupt-enable bit SYNCIE are all located in bit 0 of their respective registers (BSR,

BSRL, and BSRIE).

When set, most latched status register bits can cause an interrupt on the

INT pin if the corresponding interrupt-

enable register bit is also set. Most latched status register bits have an associated real-time status register bit.

Information registers can contain a mix of real-time and latched status bits, none of which can cause an interrupt.

Table 6-B. Status Register Set Example

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BSR

N/A

RA1

RA0

N/A

BBCO

BECO

SYNC

BSRL

N/A

RA1L

RA0L

BEDL

BBCOL

BECOL

SYNCL

BSRIE

N/A

BEDIE

BBCOIE

BECOIE

SYNCIE

Figure 6-1. Status Register Interrupt Flow

EVENT

LATCHED STATUS REGISTER

SET ON EVENT DETECT

CLEAR ON WRITE LOGIC 1

INT ENABLE

SRL

INT

OTHER INT

SOURCE

REAL-TIME STATUS

LATCHED STATUS

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