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DS3141 Datasheet(PDF) 48 Page - Dallas Semiconductor |
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DS3141 Datasheet(HTML) 48 Page - Dallas Semiconductor |
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48 / 88 page ![]() DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers 48 of 88 Register Name: BCR4 Register Description: BERT Control Register 4 Register Address: 33h Bit # 7 6 5 4 3 2 1 0 Name AWC7 AWC6 AWC5 AWC4 AWC3 AWC2 AWC1 AWC0 Default 0 0 0 0 0 0 0 0 Bits 0 to 7: Alternating Word Count Rate (AWC[7:0]). When the BERT is programmed in the alternating word mode, it transmits the word in register RP[15:0] a number of times equal to AWC[7:0] + 1 and then transmits the word loaded in RP[31:16] the same number of times. The valid count range is from 00h to FFh. These bits are ignored if the BERT is programmed for a pseudorandom pattern or a repetitive pattern. AWC VALUE ALTERNATING COUNT ACTION 00h Send the word in RP[15:0] 1 time followed by the word in RP[31:16] 1 time… 01h Send the word in RP[15:0] 2 times followed by the word in RP[31:16] 2 times… 02h Send the word in RP[15:0] 3 times followed by the word in RP[31:16] 3 times… . . . . . . FFh Send the word in RP[15:0] 256 times followed by the word in RP[31:16] 256 times… Register Name: BSR Register Description: BERT Status Register Register Address: 38h Bit # 7 6 5 4 3 2 1 0 Name N/A N/A RA1 RA0 N/A BBCO BECO SYNC Default — — — — — — — — Bit 0: Synchronization Status (SYNC). This real-time status bit is set when the incoming pattern matches for 32 consecutive bit positions. SYNC bit is cleared when six or more bits out of 64 are received in error. Bit 1: BERT Error-Counter Overflow (BECO). This real-time status bit is set when the 24-bit BERT error counter (BEC) saturates. BECO is cleared when BCR1:LC is toggled to load the error counts. Bit 2: BERT Bit-Counter Overflow (BBCO). This real-time status bit is set when the 32-bit BERT bit counter (BBC) saturates. BBCO is cleared when BCR1:LC is toggled to load the error counts. Bit 4: Receive All Zeros (RA0). This real-time status bit is set when 32 consecutive 0s are received. RA0 is cleared when a 1 is received. Bit 5: Receive All Ones (RA1). This real-time status bit is set when 32 consecutive 1s are received. RA1 is cleared when a 0 is received. |
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