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DS3141 Datasheet(PDF) 44 Page - Dallas Semiconductor |
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DS3141 Datasheet(HTML) 44 Page - Dallas Semiconductor |
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44 / 88 page ![]() DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers 44 of 88 Register Name: CPCR1 Register Description: CP-Bit Parity Error Count Register 1 Register Address: 28h Bit # 7 6 5 4 3 2 1 0 Name CPE7 CPE6 CPE5 CPE4 CPE3 CPE2 CPE1 CPE0 Default 0 0 0 0 0 0 0 0 Register Name: CPCR2 Register Description: CP-Bit Parity Error Count Register 2 Register Address: 29h Bit # 7 6 5 4 3 2 1 0 Name CPE15 CPE14 CPE13 CPE12 CPE11 CPE10 CPE9 CPE8 Default 0 0 0 0 0 0 0 0 Bits 0 to 15: CP-Bit Parity Error Count (CPE[15:0]). This count register contains the value of the internal CP-bit parity error counter latched during the last error counter update. The internal counter counts the number of DS3 CP-bit parity errors. In E3 mode or M23 DS3 mode this counter is meaningless and should be ignored. A CP-bit parity error is defined as an occurrence when the majority-decoded state of the three CP bits does not match the parity calculation made on the information bits. Through the ECC control bit in the T3E3CR2 register, the counter can be configured to either continue counting CP-bit parity bit errors during an OOF event or not. Register Name: FEBECR1 Register Description: Far-End Block Error Count Register 1 Register Address: 2Ah Bit # 7 6 5 4 3 2 1 0 Name FEBE7 FEBE6 FEBE5 FEBE4 FEBE3 FEBE2 FEBE1 FEBE0 Default 0 0 0 0 0 0 0 0 Register Name: FEBECR2 Register Description: Far-End Block Error Count Register 2 Register Address: 2Bh Bit # 7 6 5 4 3 2 1 0 Name FEBE15 FEBE14 FEBE13 FEBE12 FEBE11 FEBE10 FEBE9 FEBE8 Default 0 0 0 0 0 0 0 0 Bits 0 to 15: Far-End Block Error Count (FEBE[15:0]). This count register contains the value of the internal FEBE counter latched during the last error counter update. The internal counter counts the number of DS3 far-end block errors (FEBE). In E3 mode or M23 DS3 mode this counter is meaningless and should be ignored. A FEBE is defined as an occurrence when the three received FEBE bits do not equal 111. Through the ECC control bit in the T3E3CR2 register, the counter can be configured to either continue counting FEBE occurrences during an OOF event or not. |
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