DS3141 datasheet(14/88 Pages) DALLAS

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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

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5.5 CPU Bus Interface Pins

NAME

I/O

FUNCTION

MOT

Motorola Bus Mode Select. This pin controls whether the CPU bus operates in Intel mode or in Motorola

mode.

0 = CPU bus is in Intel mode

1 = CPU bus is in Motorola mode

D[7:0]

I/O

CPU Bus Data. The host processor accesses the devices’ internal registers through this bus. These pins

are outputs during reads and inputs otherwise. D7 is the MSB; D0 is the LSB.

A[9:0]

CPU Bus Address. The host processor specifies the address of the internal register to be accessed by this

bus. Pins A[9:8] specify the framer to be accessed. In multiplexed bus applications, the A[7:0] pins should

be connected to the D[7:0] pins, and A[9:0] must have a valid register address when the ALE pin goes low.

A9 is the MSB; A0 is the LSB.

ALE

CPU Bus Address Latch Enable. This pin controls the address latch for the A[9:0] inputs. When ALE is high,

the latch is transparent. On the falling edge of ALE, the latch samples and holds the A[9:0] inputs. In

nonmultiplexed bus applications, ALE should be wired high. In multiplexed bus applications, A[7:0] should

be connected to D[7:0], and the falling edge of ALE latches the address.

CPU Bus Chip Select, Active Low. The host processor selects the device for read or write access by driving

this pin low.

WR (R/W)

CPU Bus Write Enable (CPU Bus Read/Write Select), Active Low. In Intel mode (MOT = 0),

WR controls

write accesses to the device. In Motorola mode (MOT = 1), R/

W specifies whether a read or a write access

is to occur.

RD (DS)

CPU Bus Read Enable (CPU Bus Data Strobe), Active Low. In Intel mode (MOT = 0),

RD controls read

accesses to the device. In Motorola mode (MOT = 1),

DS controls both read and write accesses to the

device, while the R/

W pin specifies the type of access.

INT

CPU Bus Interrupt, Open Drain, Active Low. This pin is driven low by the device if one or more unmasked

interrupt sources within the device are active.

INT remains low until the interrupt is serviced or masked.

SCLK

System Clock. An ungapped clock with frequency between 33MHz and 52MHz must be provided to this pin

to run certain logic in the CPU bus port. The use of this clock allows the transmit and receive clocks (TICLK

and RCLK) to be gapped, if desired, without affecting the CPU bus timing. This pin can be connected to

TICLK or RCLK if the signal on one of those pins is an ungapped clock.

5.6 JTAG Interface Pins

NAME

I/O

FUNCTION

JTCLK

JTAG IEEE 1149.1 Test Serial Clock. This pin is used to shift data into JTDI on the rising edge and out of

JTDO on the falling edge. If not used, this pin should be wired high.

JTDI

JTAG IEEE 1149.1 Test Serial-Data Input (Internal 10k

W Pullup). Test instructions and data are clocked in

on this pin on the rising edge of JTCLK. If not used, JTDI should be left unconnected or driven high.

JTDO

JTAG IEEE 1149.1 Test Serial-Data Output. Test instructions are clocked out of this pin on the falling edge

of JTCLK. If not used, JTDO should be left open-circuited. This pin is in tri-state mode after

JTRST is

activated.

JTRST

JTAG IEEE 1149.1 Test Reset (Active Low, Internal 10k

W Pullup). This pin is used to asynchronously reset

the test access port controller. At power-up,

JTRST must be driven low and then high. This action sets the

device into the boundary scan bypass mode, allowing normal device operation. If boundary scan is not

used, this pin should be held low.

JTMS

JTAG IEEE 1149.1 Test Mode Select (Internal 10k

W Pullup). This pin is sampled on the rising edge of

JTCLK and is used to place the test port into the various defined IEEE 1149.1 states. If not used, JTMS

should be left unconnected or driven high.

5.7 Supply, Test, and Reset Pins

NAME

I/O

FUNCTION

RST

Global Hardware Reset (Active Low). When this pin is driven low, all the framers in the device are reset and all

the internal registers are forced to their default values. The device is held in the reset state as long as this pin

is low. The clocks (TICLK and RCLK) must be stable and in spec before this pin is driven high. The device

registers can be configured for operation after the reset is deactivated.

TEST

Factory Test Enable (Active Low, Internal 10k

W Pullup). This pin should be left open-circuited.

HIZ

High-Z Control (Active Low, Internal 10k

W Pullup). When this pin is low and JTRST is low, all outputs go to the

high-impedance mode. This pin can be left open-circuited by the user.

VSS

Digital Ground Reference. All VSS pins should be wired together.

VDD

Digital Positive Supply. 3.3V (

±5%). All VDD pins should be wired together.

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