DS3141 datasheet(60/88 Pages) DALLAS

60 / 88 page

DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

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HIR

HDLC Information Register

57h

Bit #

Name

N/A

REMPTY

TEMPTY

TFL3

TFL2

TFL1

TFL0

Default

—

Note: Bits in this information register cannot cause an interrupt to occur.

Bits 0 to 3: Transmit FIFO Level (TFL[3:0]). These real-time status bits indicate the current depth of the transmit

FIFO in 16-byte increments.

TFL3

TFL2

TFL1

TFL0

TRANSMIT FIFO

LEVEL (BYTES)

Empty to 15

16 to 31

32 to 47

48 to 63

64 to 79

80 to 95

96 to 111

112 to 127

128 to 143

144 to 159

160 to 175

176 to 191

192 to 207

208 to 223

224 to 239

240 to 256

Bit 4: Transmit FIFO Empty (TEMPTY). This real-time status bit is set when the transmit FIFO is empty and

cleared when the transmit FIFO contains one or more bytes.

Bit 5: Receive FIFO Empty (REMPTY). This real-time status bit is set when the receive FIFO is empty and cleared

when the receive FIFO contains one or more bytes.

DS3141 Datasheet(PDF) 60 Page - Dallas Semiconductor

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