DS3141 datasheet(37/88 Pages) DALLAS

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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

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T3E3SRL

DS3/E3 Status Register Latched

19h

Bit #

Name

COFAL

N/A

SEFL

T3IDLEL

RAIL

AISL

OOFL

LOSL

Default

—

Note: See Figure 7-5 for details on the interrupt logic for the status bits in the T3E3SRL register.

Bit 0: Loss-of-Signal Occurrence Latched (LOSL). This latched status bit is set to 1 when the LOS status bit in

the T3E3SR register changes state (low to high or high to low). LOSL is cleared when the host processor writes a 1

to it. When LOSL is set, it can cause a hardware interrupt to occur if the LOSIE bit in the T3E3SRIE register and

the T3E3IE bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is cleared or one or

both of the interrupt-enable bits are cleared. See the note in the LOS status bit description for further information.

Bit 1: Out-of-Frame Occurrence Latched (OOFL). This latched status bit is set to 1 when the OOF status bit in

the T3E3SR register changes state (low to high or high to low). OOFL is cleared when the host processor writes a

1 to it. When OOFL is set, it can cause a hardware interrupt to occur if the OOFIE bit in the T3E3SRIE register and

the T3E3IE bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is cleared or one or

both of the interrupt-enable bits are cleared.

Bit 2: Alarm Indication Signal Detected Latched (AISL). This latched status bit is set to 1 when the AIS status

bit in the T3E3SR register changes state (low to high or high to low). AISL is cleared when the host processor

writes a 1 to it. When AISL is set, it can cause a hardware interrupt to occur if the AISIE bit in the T3E3SRIE

or one or both of the interrupt-enable bits are cleared.

Bit 3: Remote Alarm Indication Detected Latched (RAIL). This latched status bit is set to 1 when the RAI status

bit in the T3E3SR register changes state (low to high or high to low). RAIL is cleared when the host processor

writes a 1 to it. When RAIL is set, it can cause a hardware interrupt to occur if the RAIIE bit in the T3E3SRIE

or one or both of the interrupt-enable bits are cleared.

Bit 4: DS3 Idle-Signal-Detected Latched (T3IDLEL). This latched status bit is set to 1 when the T3IDLE status bit

in the T3E3SR register changes state (low to high or high to low). T3IDLEL is cleared when the host processor

writes a 1 to it. When T3IDLEL is set, it can cause a hardware interrupt to occur if the T3IDLEIE bit in the

T3E3SRIE register and the T3E3IE bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit

is cleared or one or both of the interrupt-enable bits are cleared.

Bit 5: Severely Errored Frame Detected Latched (SEFL). This latched status bit is set to 1 when the SEF status

bit in the T3E3SR register changes state (low to high or high to low). SEFL is cleared when the host processor

writes a 1 to it. When SEFL is set, it can cause a hardware interrupt to occur if the SEFIE bit in the T3E3SRIE

or one or both of the interrupt-enable bits are cleared.

Bit 7: Change-of-Frame Alignment Latched (COFAL). This latched status bit is set to 1 when the DS3/E3 framer

has experienced a change of frame alignment (COFA). A COFA occurs when the framer achieves synchronization

in a different alignment than it had previously. If the framer has never acquired synchronization before, then this

status bit is meaningless. COFAL is cleared when the host processor writes a 1 to it and is not set again until the

framer has lost synchronization and reacquired synchronization in a different alignment. When COFAL is set, it can

cause a hardware interrupt to occur if the COFAIE bit in the T3E3SRIE register and the T3E3IE bit in the MSRIE

register are both set to 1. The interrupt is cleared when this bit is cleared or one or both of the interrupt-enable bits

are cleared.

DS3141 Datasheet(PDF) 37 Page - Dallas Semiconductor

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