DS3141 datasheet(74/88 Pages) DALLAS

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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

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11.

AC TIMING CHARACTERISTICS

All AC timing characteristics are specified with a 50pF capacitive load on the D[7:0] and

INT pins, and a 25pF

capacitive load on all other output pins, VIH = VDD and VIL = VSS. The voltage threshold for all timing measurements

is VDD/2.

11.1 System Interface Timing

Table 11-A. Data Path Timing

(VDD = 3.3V

±5%, TA = -40°C to +85°C.) (Figure 11-1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

(Note 1)

29.0

29.1

(Note 2)

22.0

22.4

CLK Clock Period

(Note 3)

19.0

19.3

CLK Clock Duty Cycle

t2/t1

CLK in to DIN Setup Time

(Note 4)

3.0

CLK in to DIN Hold Time

(Note 4)

1.0

CLK in to DOUT Delay

(Note 5)

2.0

CLK out to DOUT Delay

(Notes 6, 7)

2.0

7.0

CLK in to CLK OUT Delay

(Note 8)

Asynchronous Input High, Low Time

t8, t9

(Note 9)

200

Asynchronous Input Period

t10

(Note 9)

1000

Note 1: E3 mode, nongapped 34.368MHz clock.

Note 2: DS3 mode, nongapped 44.736MHz clock.

Note 3: DS3 mode, gapped 51.84MHz clock.

Note 4: TICLK input to TDAT, TOH, TOHEN, and TSOF inputs; RCLK input to RPOS and RNEG inputs.

Note 5: TICLK input to TDEN (data-enable mode) and TSOF outputs.

Note 6: ROCLK output to RDAT, RDEN (data-enable mode) and RSOF outputs; TCLK output to TPOS and TNEG outputs.

Note 7: RGCLK (gapped clock mode) output to RDAT and RSOF outputs; TDEN/TGCLK (gapped or constant clock mode) output to TSOF

output.

Note 8: TICLK input to TDEN/TGCLK (gapped clock or constant clock mode) outputs; RCLK input to ROCLK output.

Note 9: TMEI, RECU, and

RST inputs.

Table 11-B. Line Loopback Timing

(VDD = 3.3V

±5%, TA = -40°C to +85°C.) (Figure 11-2)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Skew on RPOS to TPOS Path with

Respect to RCLK to TCLK Path

t2 - t1

3.0

Skew on RNEG to TNEG path with

Respect to RCLK to TCLK Path

t2 - t1

3.0

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