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DS3141 Datasheet(PDF) 47 Page - Dallas Semiconductor |
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DS3141 Datasheet(HTML) 47 Page - Dallas Semiconductor |
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47 / 88 page ![]() DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers 47 of 88 Register Name: BCR2 Register Description: BERT Control Register 2 Register Address: 31h Bit # 7 6 5 4 3 2 1 0 Name N/A PS2 PS1 PS0 RPL3 RPL2 RPL1 RPL0 Default — 0 0 0 0 0 0 0 Bits 0 to 3: Repetitive Pattern Length (RPL[3:0]). RPL3 is the MSB and RPL0 is the LSB of a nibble that describes how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the BERT is programmed for a pseudorandom pattern or an alternating word pattern. To create repetitive patterns fewer than 17 bits in length, the user must set the length to an integer multiple of the desired length that is less than or equal to 32. For example, to create a 6-bit pattern, set the length to 18 (0001), 24 (0111), or 30 (1101). Length Code Length Code Length Code Length Code 17 bits 0000 18 bits 0001 19 bits 0010 20 bits 0011 21 bits 0100 22 bits 0101 23 bits 0110 24 bits 0111 25 bits 1000 26 bits 1001 27 bits 1010 28 bits 1011 29 bits 1100 30 bits 1101 31 bits 1110 32 bits 1111 Bits 4 to 6: Pattern Select (PS[2:0]). This field specifies the type of pattern to be generated. After configuring these bits, the TC bit in the BCR1 register must be toggled to reconfigure the pattern generator. PS[2:0] PATTERN TAPS SPECIFICATION TINV RINV 000 Repetitive Pattern — — — — 001 Alternating Word Pattern — — — — 010 2 15 - 1 14, 15 ITU O.151 (for DS3) 1 1 011 2 20 - 1 QRSS 17, 20 T1.403 0 0 100 2 23 - 1 18, 23 ITU O.151 (for E3) 1 1 101 2 31 - 1 28, 31 (none) 0 0 110 Invalid — — — — 111 Invalid — — — — Register Name: BCR3 Register Description: BERT Control Register 3 Register Address: 32h Bit # 7 6 5 4 3 2 1 0 Name N/A N/A N/A N/A EIB2 EIB1 EIB0 SBE Default — — — — 0 0 0 0 Bit 0: Single Bit-Error Insert (SBE). A low-to-high transition creates a single bit error. Must be cleared and set again for a subsequent bit error to be inserted. Bits 1 to 3: Error Insert Bits (EIB[2:0]). Automatically insert bit errors at the prescribed rate into the generated data pattern. Useful for verifying error detection operation. EIB[2:0] ERROR RATE INSERTED 000 No errors automatically inserted 001 10 –1 (1 error per 10 bits) 010 10 –2 (1 error per 100 bits) 011 10 –3 (1 error per 1000 bits) 100 10 –4 (1 error per 10,000 bits) 101 10 –5 (1 error per 100,000 bits) 110 10 –6 (1 error per 1,000,000 bits) 111 10 –7 (1 error per 10,000,000 bits) |
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