DS3141 datasheet(52/88 Pages) DALLAS

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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

52 of 88

BBCR1

BERT Bit Counter Register 1 (lower byte)

40h

Bit #

Name

BBC7

BBC6

BBC5

BBC4

BBC3

BBC2

BBC1

BBC0

Default

BBCR2

BERT Bit Counter Register 2

41h

Bit #

Name

BBC15

BBC14

BBC13

BBC12

BBC11

BBC10

BBC9

BBC8

Default

BBCR3

BERT Bit Counter Register 3

42h

Bit #

Name

BBC23

BBC22

BBC21

BBC20

BBC19

BBC18

BBC17

BBC16

Default

BBCR4

BERT Bit Counter Register 4 (upper byte)

43h

Bit #

Name

BBC31

BBC30

BBC29

BBC28

BBC27

BBC26

BBC25

BBC24

Default

Bits 0 to 31: BERT Bit Counter (BBC[31:0]). The BBCR registers are loaded with the value of the internal BERT

bit counter when the LC control bit in the BCR1 register is toggled. This 32-bit counter increments for each data bit

received. The bit counter starts counting when the BERT goes into receive synchronization (SYNC = 1) and

continues counting even if the BERT loses sync. The bit counter saturates and does not roll over. Upon saturation,

the BBCO status bit in the BSR register is set. When the LC bit is toggled, the bit count is loaded into the BBCR

registers and the internal bit counter is cleared. If the BERT is in sync when LC is toggled, the bit counter continues

to count up from zero. If the BERT is out of sync when LC is toggled, the bit counter is held at zero until the BERT

regains sync. The host processor should toggle LC after the BERT has synchronized and then toggle LC again

when the error-checking period is complete. If the framer loses synchronization during this period, then the

counting results are suspect.

DS3141 Datasheet(PDF) 52 Page - Dallas Semiconductor

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