DS3141 datasheet(72/88 Pages) DALLAS

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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

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SAMPLE/PRELOAD. SAMPLE/PRELOAD is a mandatory instruction for the IEEE 1149.1 specification. This

instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register

without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also

allows the device to shift data into the boundary scan register through JTDI using the Shift-DR state.

EXTEST. EXTEST allows testing of all interconnections to the device. When the EXTEST instruction is latched in

the instruction register, the following actions occur. Once enabled by the Update-IR state, the parallel outputs of all

digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The Capture-DR

samples all digital inputs into the boundary scan register.

BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO

through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device’s normal

operation.

IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the identification test

JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially

through JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel

output.

HIGHZ. All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI

and JTDO.

CLAMP. All digital output pins output data from the boundary scan parallel output while connecting the bypass

Table 9-B. JTAG ID Code

DEVICE

REVISION

DEVICE CODE

MANUFACTURER’S CODE

REQUIRED

DS3141

Consult factory

0000000000010001

00010100001

DS3142

Consult factory

0000000000010010

00010100001

DS3143

Consult factory

0000000000010011

00010100001

DS3144

Consult factory

0000000000010100

00010100001

9.3 JTAG Scan Registers

IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An

optional test register, the identification register, has been included in the design and is used with the IDCODE

instruction and the Test-Logic-Reset state of the TAP controller.

Bypass Register

The bypass register is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that

provides a short path between JTDI and JTDO.

Identification Register

The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is

selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. The device

ID code always has a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and

number of continuation bytes, followed by 16 bits for the device and 4 bits for the version.

Boundary Scan Register

The boundary scan register contains a shift register path and a latched parallel output for all control cells and digital

I/O cells.

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