DS3141 datasheet(25/88 Pages) DALLAS

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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

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MC3

Master Configuration Register 3

03h

Bit #

Name

TDENMS

TSOFC

TOHENI

TOHI

TSOFI

TICLKI

TDATI

TDENI

Default

Bit 0: TDEN Invert Enable (TDENI)

0 = do not invert the TDEN/TGCLK signal (normal mode)

1 = invert the TDEN/TGCLK signal (inverted mode)

Bit 1: TDAT Invert Enable (TDATI)

0 = do not invert the TDAT signal (normal mode)

1 = invert the TDAT signal (inverted mode)

Bit 2: TICLK Invert Enable (TICLKI)

0 = do not invert the TICLK signal (normal mode)

1 = invert the TICLK signal (inverted mode)

Bit 3: TSOF Invert Enable (TSOFI)

0 = do not invert the TSOF signal (normal mode)

1 = invert the TSOF signal (inverted mode)

Bit 4: TOH Invert Enable (TOHI)

0 = do not invert the TOH signal (normal mode)

1 = invert the TOH signal (inverted mode)

Bit 5: TOHEN Invert Enable (TOHENI)

0 = do not invert the TOHEN signal (normal mode)

1 = invert the TOHEN signal (inverted mode)

Bit 6: Transmit Start-of-Frame I/O Control (TSOFC). When this bit is logic 1, the TSOF pin is an output and

pulses for the last TICLK cycle of each frame. When this bit is 0, the TSOF pin is an input, and the device uses it to

determine the frame boundaries. See Figure 5-1 for functional timing information.

0 = TSOF is an input (reset default as input)

1 = TSOF is an output

Bit 7: Transmit Data-Enable Mode Select (TDENMS). When this bit is logic 0, the TDEN/TGCLK output has the

TDEN (data enable) function. TDEN asserts during payload bit times and de-asserts during overhead bit times.

When this bit is logic 1, TDEN/TGCLK has the TGCLK (gapped clock) function. TGCLK pulses during payload bit

times and is suppressed during overhead bit times. The TCCLK control bit in the MC2 register has precedence

over this control bit. See Figure 5-1 for functional timing information.

0 = TDEN (data enable) mode

1 = TGCLK (gapped clock) mode

DS3141 Datasheet(PDF) 25 Page - Dallas Semiconductor

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