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DP83261 Datasheet(PDF) 117 Page - National Semiconductor (TI) |
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DP83261 Datasheet(HTML) 117 Page - National Semiconductor (TI) |
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117 / 132 page ![]() 80 Electrical Characteristics (Continued) 842 Clock Signals Symbol Parameter Min Max Units T21 LSC to LBC Lead Time (Skew Left) b 46 ns T22 LSC Pulse Width High 12 ns T23 LSC Pulse Width Low 21 ns T24 LBC Pulse Width High 35 45 ns T25 LBC Pulse Width Low 35 45 ns TLF10387 – 32 FIGURE 8-5 Clock Signals 843 PHY Interface Symbol Parameter Min Max Units T26 PHY Data Input Setup 15 ns T27 PHY Data Input Hold 5 ns T28 PHY Data Sustain 10 ns T29 PHY Data Valid 45 ns TLF10387 – 33 Note All setup and hold testing is done on single edges only (ie no combined setuphold testing is done for pulse signals This implies that the signal makes only one low to high or high to low transition per cycle) FIGURE 8-6 PHY Interface Timing 117 |
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