FXLS93421 datasheet(166/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Source

identification

(4 Bits)

Keep alive

counter (2 Bits)

Status (4 Bits)

Sensor data

(10 Bits)

Non-direct seed

8-bit CRC

0x2

0x0

0x1FE

0x02

0x70

0x3

0x1

0x0

0x20D

0x03

0xB0

0x4

0x0

0x1EA

0x04

0x5F

Table 256. Periodic data collection mode - CRC calculation examples...continued

12.4.3 DSI3 periodic data collection mode timing

A timing diagram for periodic data collection mode is shown in Figure 76. Timing

parameters are specified in Section 10.11.

aaa-030660

BUS_I

tSTART_PDCM, PDCM_RSPT[12;0]

tCMD_BitTime

Iq + 2 x IRESP

Iq + IRESP

CMD_Start

response

current

1st

symbol

24th

symbol

tCHIP_PDCM

tPER_PDCM

tSLEW1_RESP

tSLEW2_RESP

Figure 76. Periodic data collection mode timing diagram

12.4.4 Background diagnostic mode response transmission

12.4.4.1 Symbol encoding

The Background Diagnostic Mode response symbol encoding is the same as the symbol

encoding used for Command and Response Mode responses and is described in

Section 12.3.2.1.

12.4.4.2 Response message format

The Background Diagnostic Mode response message format is the same as the format

used for Command and Response Mode responses and is described in Section 12.3.2.2.

• If a complete 32-bit command is received and decoded to a valid Command and

Response Mode command, the device provides a Background Diagnostic Mode

response.

• Responses are initiated by the master transmitting 1-bit Broadcast Read Commands

following a completed Background Diagnostic Mode command transmission.

• Responses are transmitted in one or two symbol fragments (depending on the state

of the BDM_FRAGSIZE bit) following the 1-bit Broadcast Read Command, using the

same timing window within the frame that the Background Diagnostic Mode Command

used.

• Responses are transmitted if and only if Broadcast Read Commands are received.

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

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