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FXLS93421 Datasheet(PDF) 162 Page - NXP Semiconductors

Part # FXLS93421
Description  Dual channel inertial sensor
PDF  254 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS93421 Datasheet(HTML) 162 Page - NXP Semiconductors

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NXP Semiconductors
FXLS9xxxx
Dual channel inertial sensor
Address
Command
Data
PA3
PA2
PA1
PA0
C3
C2
C1
C0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CRC
PA[3]
PA[2]
PA[1]
PA[0]
0
0
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
PA[3]
PA[2]
PA[1]
PA[0]
0
1
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
PA[3]
PA[2]
PA[1]
PA[0]
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
PA[3]
PA[2]
PA[1]
PA[0]
0
1
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
PA[3]
PA[2]
PA[1]
PA[0]
0
1
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
PA[3]
PA[2]
PA[1]
PA[0]
1
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
PA[3]
PA[2]
PA[1]
PA[0]
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
PA[3]
PA[2]
PA[1]
PA[0]
1
1
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
PA[3]
PA[2]
PA[1]
PA[0]
1
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
PA[3]
PA[2]
PA[1]
PA[0]
1
1
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
PA[3]
PA[2]
PA[1]
PA[0]
1
1
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
Table 249. Reserved commands...continued
Bit field
Definition
PA[3:0]
DSI physical address. This field contains the physical address. This field must match the PADDR[3:0] bits
in the PHYSADDR register. Otherwise, the command is ignored.
C[3:0]
Invalid Commands
x
Don't Care
Table 250. Reserved commands description
Address
Command
Data
PA3 PA2 PA1 PA0
C3
C2
C1
C0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CRC
PA[3] PA[2] PA[1] PA[0] C[3]
C[2]
C[1]
C[0]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
Table 251. Reserved command response format
Bit field
Definition
PA[3:0]
DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register.
C[3:0]
Reserved Command Echo
Table 252. Reserved command response format description
12.4 DSI3 periodic data collection mode and background diagnostic mode
When the ENDINIT bit in the DEVLOCK_WR register is set, periodic data collection
mode is enabled and the optional background diagnostic mode is enabled.
12.4.1 DSI3 periodic data collection mode and background diagnostic mode
command reception
When periodic data collection mode is enabled, the device will decode the DSI3
broadcast read command as well as background diagnostic mode command fragments
as described below.
FXLS9xxxx
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6 — 8 February 2021
162 / 254



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