FXLS93421 datasheet(158/254 Pages) NXP

158 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

the PHYSADDR register and a valid CRC is calculated, the device responds to the

command.

The device ignores the Register Read command if the command is sent to any other

physical address, including the DSI Global Device Address of '0000'.

The Register Read command uses the byte address definitions shown in Section 11.1.

The Register Read response includes the register contents at the time the Register Read

command decode is complete. Readable registers along with their byte addresses are

shown in Section 11.1. If an attempt is made to read a register that is not readable, the

device will respond with all zero data.

Address

Command

Data

PA3 PA2 PA1 PA0

D15

D14

D13

D12

D11

D10

CRC

PA[3] PA[2] PA[1] PA[0]

RA[7] RA[6] RA[5] RA[4] RA[3] RA[2] RA[1]

8 bits

Table 232. Register read command format

Bit field

Definition

PA[3:0]

DSI physical address. This field contains the physical address. This field must match the PADDR[3:0] bits

in the PHYSADDR register. Otherwise, the command is ignored.

C[3:0]

RA[7:1]

RA[7:1] contains the upper 7 bits of the byte address for the register to be read.

Table 233. Register read command format description

Address

Command

Data

PA3 PA2 PA1 PA0

D15

D14

D13

D12

D11

D10

CRC

PA[3] PA[2] PA[1] PA[0]

RD[15] RD[14] RD[13] RD[12] RD[11] RD[10] RD[9] RD[8] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] 8 bits

Table 234. Register read command: response format

Bit field

Definition

PA[3:0]

DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register.

C[3:0]

RD[15:8]

The data contained in the register addressed by RA[7:1] + 1 (High Byte)

RD[7:0]

The data contained in the register addressed by RA[7:1] + 0 (Low Byte)

Table 235. Register read command: response format description

A register read command to a register address outside the addresses listed in

Section 11.1 will result in a valid response. The data for the registers will be '0x0000'.

12.3.4.2 Register write command

The device supports the Register Write command as a device address specific

command. If the PA[3:0] field in the command matches the value in the PADDR[3:0] bits

of the PHYSADDR register, the device will execute the register write and respond to the

command.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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