FXLS93421 datasheet(154/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

5. If the shift register contains a value other than zero, the CRC is incorrect.

The CRC polynomial and seed for Command and Response Mode are shown in

Table 224 .

Mode

Default polynomial

Non-direct seed

Command and Response Mode

x8 + x5 + x3 + x2 + x + 1

1111 1111

Table 224. Command and response mode command CRC

Some example CRC calculations are shown in Table 225 .

Physical address

Command

Extended data

Non-direct seed

8-bit CRC

0x01

0x08

0x11

0x86

0xFF

0xB0

0x02

0x01

0x25

0xFF

0x38

0x03

0x0F

0x1A

0x41

0xFF

0x2C

0x04

0x01

0xFF

0xD4

Table 225. Command and response mode - CRC calculation examples

12.3.2 DSI3 command and response mode response transmission

An example command and response mode response is shown in Figure 71. The

response consists of 32 bits of data broken up into multiple fields as described in

Section 12.3.2.2.

response

current

1st symbol

aaa-030655

Figure 71. Command and response mode response example

Physical address

Command

Extended data

Error checking

PA3 PA2 PA1 PA0 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0

Table 226. Command and response mode response example

12.3.2.1 Symbol encoding

The device response to a Command and Response Mode Command uses multi-level

source coding where data nibbles are first encoded into symbols and then the symbols

are encoded into current levels. The symbols are assembled from three consecutive

three-level current pulses called chips. Within a symbol there are 3 consecutive chips

that can assume one of three discrete current levels as described in Section 10.5: iq, iq +

iRESP, and iq + 2 x iRESP. Figure 72 shows the chip trans-missions and an example of a 3

symbol (9 chip), 12-bit data packet.

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

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