FXLS93421 datasheet(156/254 Pages) NXP

156 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Encoded data (4 Bits)

Symbol transmitted

Binary

HEX

1st Chip

2nd Chip

3rd Chip

1111

Where:

0 = iq

1 = iRESP

2 = 2 x iRESP

Table 227. Symbol mapping...continued

12.3.2.2 Response message format

The command and response mode response format is shown in Table 228.

Physical address

Command

CRC

PA[3:0]

CMD[3:0]

RD1[7:0]

RD[7:0]

CRC[7:0]

Table 228. Command and response mode - response format

Field

Length (Bits)

Definition

PA[3:0]

Physical Address

Matches the value in the PADDR[3:0] of the PHYSADDR register

CMD[3:0]

An echo of the received command

ED[7:0]

The data contained in the register addressed by RA[7:1] + 1 (High Byte, see

Section 12.3.4)

RD[7:0]

The data contained in the register addressed by RA[7:1] + 0 (Low Byte, see

Section 12.3.4)

CRC[7:0]

Error Checking (see Section 12.3.2.3)

Table 229. Command and response mode - field definitions

12.3.2.3 Error checking

The device calculates a CRC on the entire 32-bits of each response. Message data is

entered into the CRC calculator MSB first, consistent with the transmission order of the

message.

The CRC Encoding procedure is:

1. A seed value is preset into the least significant bits of the shift register.

2. Using a serial CRC calculation method, the transmitter rotates the transmitted

message into the least significant bits of the shift register, MSB first.

3. Following the transmitted message, the transmitter feeds eight zeros into the shift

4. When the last zero is fed into the input adder, the shift register contains the CRC.

5. The CRC is transmitted.

The CRC polynomial and seed for Command and Response Mode are shown in

Table 230.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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