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FXLS93421 Datasheet(PDF) 153 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 153 Page - NXP Semiconductors |
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153 / 254 page ![]() NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Physical address Command Extended data Register data Error checking PA3 PA2 PA1 PA0 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0 Table 221. Command and response mode example command descriptions 12.3.1.1 Bit encoding Figure 70 shows the bit encoding used for Command and Response Mode Commands from the Master device. 0 0 VHIGH VLOW 0 1 1 0 1 1 aaa-030654 Figure 70. Command and response mode command bit encoding 12.3.1.2 Command message format The command and response mode command format is shown in Table 222. Physical address Command Extended data Register data CRC PA[3:0] CMD[3:0] ED[7:0] RD[7:0] CRC[7:0] Table 222. Command and response mode - command format Field Length (Bits) Definition PA[3:0] 4 Physical Address. The physical address must match the value in the PADDR[3:0] of the PHYSADDR register CMD[3:0] 4 Command (see Section 12.3.4) ED[7:0] 8 Extended Data (see Section 12.3.4) RD[7:0] 8 Register Data (see Section 12.3.4) CRC[7:0] 8 Error Checking (see Section 12.3.1.3) Table 223. Command and response mode - field definitions 12.3.1.3 Error checking The device calculates an 8-bit CRC on the entire 32-bits of each command. Message data is entered into the CRC calculator MSB first, consistent with the transmission order of the message. If the calculated CRC does not match the transmitted CRC, the command is ignored and the device does not respond. The CRC decoding procedure is: 1. A seed value is preset into the least significant bits of the shift register. 2. Using a serial CRC calculation method, the receiver rotates the received message and CRC into the least significant bits of the shift register in the order received (MSB first). 3. When the calculation on the last bit of the CRC is rotated into the shift register, the shift register contains the CRC check result. 4. If the shift register contains all zeros, the CRC is correct. FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 153 / 254 |
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