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FXLS93421 Datasheet(PDF) 161 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 161 Page - NXP Semiconductors |
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161 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor PDCM Enabled? BDM_EN Command and Response Mode Periodic Data Collection Mode Background Diagnostic Mode No 0 Enabled Disabled Disabled No 1 Enabled Disabled Disabled Yes 0 Disabled Enabled Disabled Yes 1 Disabled Enabled Enabled Table 244. PDCM enable command and BDM_EN bit status Once the ENDINIT bit is set, the registers listed in Section 11.3.3 are locked and the user array read/write register array verification is enabled. The ENDINIT bit can only be cleared by a device reset. Address Command Data PA3 PA2 PA1 PA0 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CRC PA[3] PA[2] PA[1] PA[0] 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 bits Table 245. Enter periodic data collection mode command format Bit field Definition PA[3:0] DSI physical address. This field contains the physical address. This field must match the PADDR[3:0] bits in the PHYSADDR register or the Global Address of '0000'. Otherwise, the command is ignored. C[3:0] Enter PDCM Command = '1011' Table 246. Enter periodic data collection mode command format description Address Command Data PA3 PA2 PA1 PA0 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CRC PA[3] PA[2] PA[1] PA[0] 1 0 1 1 0 0 0 0 Ch[3] Ch[2] Ch[1] Ch[0] 0 0 0 0 0 0 0 0 8 bits Table 247. Enter periodic data collection mode command: response format Bit field Definition PA[3:0] DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register. Ch[3:0] CHIPTIME[3:0] in the CHIPTIME register C[3:0] Enter Periodic Data Collection Mode Command = '1011' Table 248. Enter periodic data collection mode command: response format description 12.3.4.5 Reserved commands If the PA[3:0] field in the command matches the value in the PADDR[3:0] bits of the PHYSADDR register and a valid CRC is calculated, the device will respond to reserved commands. The physical address and command will be echoed and the correct CRC are transmitted. The data included in the response is undefined. Address Command Data PA3 PA2 PA1 PA0 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CRC PA[3] PA[2] PA[1] PA[0] 0 0 0 1 x x x x x x x x x x x x x x x x 8 bits PA[3] PA[2] PA[1] PA[0] 0 0 1 0 x x x x x x x x x x x x x x x x 8 bits Table 249. Reserved commands FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 161 / 254 |
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