CEC1712 datasheet(178/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 178

 2020-2021 Microchip Technology Inc.

15.7

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

15.7.1

POWER DOMAINS

15.7.2

CLOCK INPUTS

15.7.3

RESETS

15.8

Interrupts

This section defines the interrupt Interface signals routed to the chip interrupt aggregator.

Each instance of the Hibernation Timer in the CEC1712 can be used to generate interrupts and wake-up events when

the timer decrements to zero.

15.9

Low Power Modes

The timer operates off of the 32KHz clock, and therefore will operate normally when the main oscillator is stopped.

The sleep enable inputs have no effect on the Hibernation Timer and the clock required outputs are only asserted during

15.10 EC Registers

Registers for this block are shown in the following summary table. Addresses for each register are determined by adding

the offset to the Base Address for each instance of the Hibernation Timer Block in the Block Overview and Base Address

Table in Section 3.0, "Device Inventory".

TABLE 15-1:

POWER SOURCES

Name

Description

VTR_CORE

The timer control logic and registers are all implemented on this single

power domain.

TABLE 15-2:

CLOCK INPUTS

Name

Description

32KHz

This is the clock source to the timer logic. The Pre-scaler may be used to

adjust the minimum resolution per bit of the counter.

if the main oscillator is stopped then an external 32.768kHz clock source

must be active for the Hibernation Timer to continue to operate.

TABLE 15-3:

RESET SIGNALS

Name

Description

RESET_SYS

This reset signal, which is an input to this block, resets all the logic and

registers to their initial default state.

TABLE 15-4:

INTERRUPT INTERFACE SIGNAL DESCRIPTION TABLE

Name

Direction

Description

HTIMER

Output

Signal indicating that the timer is enabled and decrements to 0. This

signal is used to generate an Hibernation Timer interrupt event.

TABLE 15-5:

Offset

00h

HTimer Preload Register

04h

HTimer Control Register

08h

HTimer Count Register

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