TAS2780 datasheet(32/97 Pages) TI

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The TAS2780 also monitors die temperature and Class-D load current and will enter Software Shutdown mode

if either of these exceed safe values. As with the TDM clock error, the IRQZ pin will assert low for these faults if

the fault interrupt mask register bit is set low for over temperature and for over current. The fault status can also

be monitored in the latched fault registers.

Die over temperature and Class-D over current errors can either be latching (for example, the device will enter

Software Shutdown until a Hardware or Software Shutdown sequence is applied) or they can be programmed to

automatically retry after a prescribed time. This behavior can be configured in the OTE_RETRY, OCE_RETRY

attempt to retry after an over temperature or over current error until the retry time period (1.5 s) has elapsed.

This prevents applying repeated stress to the device in a rapid fashion that could lead to device damage. If the

device has been cycled through a Hardware or Software Shutdown, it will only begin to operate after the retry

time period.

By default all retry features are disabled.

When exiting Software Shutdown to Active mode (for example: MODE[2:0] bits from 010b to 000b), if PVDD

under voltage is detected, the device will go back into Software Shutdown mode and an interrupt (IL_PUVLO)

will be flagged. To exit this fault user needs to clear the interrup and program the device in Software Shutdown

using MODE[2:0] bits, before making another attempt to go to Active mode.

A similar situation might occur in PWR_MODE2, if internal VBAT1S LDO undervoltage is detected and

IL_LDO_UV interrupt is flagged.

The status registers (and IRQZ pin, if enabled via the status mask register) also indicate limiter behavior

including when the limiter is activated, when PVDD is below the inflection point, when maximum attenuation has

been applied, when the limiter is in infinite hold and when the limiter has muted the audio.

In situations when the device operates in PWR_MODE2 the VBAT1S pin is supplied by an internal LDO.

Protection circuits monitor this block and generate faults in case of under voltage, over voltage or if the LDO is

over loaded. The device goes into Software Shutdown mode if one of these faults triggers.

The IRQZ pin is an open drain output that asserts low during unmasked fault conditions and therefore must be

pulled up with a resistor to IOVDD. An internal pull up resistor is provided and can be accessed (connected to

the pin) by setting the IRQZ_PU register bit high.

The IRQZ interrupt configuration can be set using IRQZ_PIN_CFG[1:0] register bits. The IRQZ_POL register bit

sets the interrupt polarity.

The INT_LTCH_CLR register bit allows to clear all the interrupt latch register bits.

Live flag registers are active only when the device is in Active mode of operation. If the device is shutdown by

I2C command or due to any fault condition described below, the live flags will be reset. Latched flags will not be

reset in this condition and available for user to read their status.

Table 8-7. Fault Interrupt Mask

Interrupt

Live Register Bit

Latch Register Bit

Mask Register Bit

Default (1 = Mask)

Temp Over 105°C

IL_TO105

IR_TO105

IM_TO105

Temp Over 115°C

IL_TO115

IR_TO115

IM_TO115

Temp Over 125°C

IL_TO125

IR_TO125

IM_TO125

Temp Over 135°C

IL_TO135

IR_TO135

IM_TO135

Over Temp Error

Device in shutdown

IR_OT

IM_OT

Over Current Error

Device in shutdown

IR_OC

IM_OC

TDM Clock Error

Device in shutdown

IR_TDMCE

IM_TDMCE

TDM Clock Error: Invalid SBCLK ratio or FS

rate

IR_TDMCEIR

TDM Clock Error: FS changed on the fly

IR_TDNCEFC

TDM Clock Error: SBCLK FS ratio changed on

the fly

IR_TDMCERC

TAS2780

SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022

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