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TAS2780 Datasheet(PDF) 17 Page - Texas Instruments |
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TAS2780 Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 97 page  8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Device Address Selection The TAS2780 operates using a TDM/I2S interface. Audio input and output are provided via the FSYNC, SBCLK, SDIN and SDOUT pins using formats including I2S, Left Justified and TDM. Configuration and status are provided via the SDA and SCL pins using the I2C protocol. The table below illustrates how to configure the device for I2C address . The peripheral addresses are shown left shifted by one bit with the R/W bit set to 0 (for example, {ADDR[6:0],1b0}). Resistors with tolerance better than 5% must be used for setting the address configuration. Table 8-2. I2C Address Selection I2C Address 0x70 0x72 0x74 0x76 0x78 0x7A 0x7C 0x7E ADDR PIN Short to GND 470 Ω to GND 470 Ω to AVDD 2.2k Ω to GND 2.2k Ω to AVDD 10 kΩ to GND 10 kΩ to AVDD Short to AVDD The TAS2780 has a global 7-bit I2C address 0x80. When enabled, the device will additionally respond to I2C commands at this address regardless of the ADDR pin settings. This is used to speed up device configuration when using multiple TAS2780 devices and programming similar settings across all devices. The I2C ACK/ NACK cannot be used during the multi-device writes since multiple devices are responding to the I2C command. The I2C CRC function should be used to ensure each device properly received the I2C commands. At the completion of writing multiple devices using the global address, the CRC at I2C_CKSUM register should be checked on each device using the local address for a proper value. The global I2C address can be disabled using I2C_GBL_EN register bit. The I2C address is detected by automatically sampling the ADDR pin when www.ti.com TAS2780 SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TAS2780 |
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