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TAS2780 Datasheet(PDF) 41 Page - Texas Instruments |
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TAS2780 Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 97 page  Bit Field Type Reset Description 3-1 SAMP_RATE[2:0] RW 4h Sample rate of the TDM bus 000b-011b = Reserved 100b = 44.1/48 kHz 101b = 88.2/96 kHz 110b-111b = Reserved 0 FRAME_START RW 1h TDM frame start polarity 0b = Low to High on FSYNC 1b = High to Low on FSYNC 8.9.14 TDM_CFG1 (page=0x00 address=0x09) [reset=02h] Bit Field Type Reset Description 7 Reserved R 0h Reserved 6 RX_JUSTIFY RW 0h TDM RX sample justification within the time slot 0b = Left 1b = Right 5-1 RX_OFFSET[4:0] RW 1h TDM RX start of frame to time slot 0 offset - number of SBCLK cycles from transiton of FSYNC 0 RX_EDGE RW 0h TDM RX capture clock polarity 0b = Rising edge of SBCLK 1b = Falling edge of SBCLK 8.9.15 TDM_CFG2 (page=0x00 address=0x0A) [reset=0Ah] Bit Field Type Reset Description 7-6 IVMON_LEN[1:0] RW 0h Sets the current and voltage data to length of 00b = 16 bits 01b = 12 bits 10b = 8 bits 11b = Reserved 5-4 RX_SCFG[1:0] RW 0h TDM RX time slot select config 00b = Mono with time slot equal to I2C address offset 01b = Mono left channel 10b = Mono right channel 11b = Stereo downmix (L+R)/2 3-2 RX_WLEN[1:0] RW 2h TDM RX word length 00b = 16 bits 01b = 20 bits 10b = 24 bits 11b = 32 bits 1-0 RX_SLEN[1:0] RW 2h TDM RX time slot length 00b = 16 bits 01b = 24 bits 10b = 32 bits 11b = Reserved 8.9.16 LIM_MAX_ATTN (page=0x00 address=0x0B) [reset=80h] Bit Field Type Reset Description 7-4 LIM_MAX_ATTN[3:0] RW 8h Limiter Maximum Attenuation 0h = 1 dB 1h = 2 dB 2h = 3 dB ... 0Eh = 15 dB 0Fh = Reserved 3-0 Reserved R 0h Reserved www.ti.com TAS2780 SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TAS2780 |
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